JPS5730077A - Accumulated instruction processing system - Google Patents

Accumulated instruction processing system

Info

Publication number
JPS5730077A
JPS5730077A JP10550080A JP10550080A JPS5730077A JP S5730077 A JPS5730077 A JP S5730077A JP 10550080 A JP10550080 A JP 10550080A JP 10550080 A JP10550080 A JP 10550080A JP S5730077 A JPS5730077 A JP S5730077A
Authority
JP
Japan
Prior art keywords
counter
controls
accumulated
output
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10550080A
Other languages
Japanese (ja)
Inventor
Masanori Mogi
Satoru Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10550080A priority Critical patent/JPS5730077A/en
Publication of JPS5730077A publication Critical patent/JPS5730077A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Data Mining & Analysis (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Algebra (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To enable effective operation, by making possible the accumulated operation if the number of processed data is smaller than the operating means of the processor. CONSTITUTION:A gate 12 controls input buses and gates 18, 14 controls 0 input from a 0 generator. A control section 15 controls gates 9, 10 and pre-shift circuits 1, 2, operation circuit 8 and post shift circuit 4. A termination processing counter 16 counts the number of cycles of the accumulated processing, and to a vector length counter 17, the number of data accumulated processing is initially set, and when 0 is counted, the subtraction afterwards is stopped. The 0 detector 18 detects when the counter 17 is 0 to produce an output. A decoder 20 gives an output to output line l when the counter 16 is at an off number and to output line l0 when even number.
JP10550080A 1980-07-31 1980-07-31 Accumulated instruction processing system Pending JPS5730077A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10550080A JPS5730077A (en) 1980-07-31 1980-07-31 Accumulated instruction processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10550080A JPS5730077A (en) 1980-07-31 1980-07-31 Accumulated instruction processing system

Publications (1)

Publication Number Publication Date
JPS5730077A true JPS5730077A (en) 1982-02-18

Family

ID=14409314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10550080A Pending JPS5730077A (en) 1980-07-31 1980-07-31 Accumulated instruction processing system

Country Status (1)

Country Link
JP (1) JPS5730077A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5947643A (en) * 1982-09-13 1984-03-17 Hitachi Ltd Arithmetic processing system
JPS6072069A (en) * 1983-09-28 1985-04-24 Nec Corp Vector operation processor
JPH01180670A (en) * 1988-01-13 1989-07-18 Hitachi Ltd Arithmetic processing system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5947643A (en) * 1982-09-13 1984-03-17 Hitachi Ltd Arithmetic processing system
JPH0313624B2 (en) * 1982-09-13 1991-02-22 Hitachi Ltd
JPS6072069A (en) * 1983-09-28 1985-04-24 Nec Corp Vector operation processor
JPS6248873B2 (en) * 1983-09-28 1987-10-15 Nippon Electric Co
JPH01180670A (en) * 1988-01-13 1989-07-18 Hitachi Ltd Arithmetic processing system

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