JPS5726459A - Glass-sealed semiconductor device - Google Patents
Glass-sealed semiconductor deviceInfo
- Publication number
- JPS5726459A JPS5726459A JP10146980A JP10146980A JPS5726459A JP S5726459 A JPS5726459 A JP S5726459A JP 10146980 A JP10146980 A JP 10146980A JP 10146980 A JP10146980 A JP 10146980A JP S5726459 A JPS5726459 A JP S5726459A
- Authority
- JP
- Japan
- Prior art keywords
- glass
- lead frame
- semiconductor device
- pellet
- sealed semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
PURPOSE:To eliminate the improper bonding of a glass-sealed semiconductor device by bending the end of a glass-sealed lead to be connected to a semiconductor pellet toward the base side. CONSTITUTION:The end of a lead frame 3 to be bonded is bent, and is contacted with the pellet mounting part of the ceramic base. When the base 1 and the lead frame 3 are bonded solderlessly via glasses 2, 2', the height of the leads become equal at the length h of the bent part. Accordingly, the improper bonding does not occur between the pellet 4 and the fine wire 5 of the lead frame 3, thereby improving the reliability.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10146980A JPS5726459A (en) | 1980-07-24 | 1980-07-24 | Glass-sealed semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10146980A JPS5726459A (en) | 1980-07-24 | 1980-07-24 | Glass-sealed semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5726459A true JPS5726459A (en) | 1982-02-12 |
Family
ID=14301572
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10146980A Pending JPS5726459A (en) | 1980-07-24 | 1980-07-24 | Glass-sealed semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5726459A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5034044A (en) * | 1988-05-11 | 1991-07-23 | General Electric Company | Method of bonding a silicon package for a power semiconductor device |
US5133795A (en) * | 1986-11-04 | 1992-07-28 | General Electric Company | Method of making a silicon package for a power semiconductor device |
-
1980
- 1980-07-24 JP JP10146980A patent/JPS5726459A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5133795A (en) * | 1986-11-04 | 1992-07-28 | General Electric Company | Method of making a silicon package for a power semiconductor device |
US5034044A (en) * | 1988-05-11 | 1991-07-23 | General Electric Company | Method of bonding a silicon package for a power semiconductor device |
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