JPS5725035A - Character display controller - Google Patents

Character display controller

Info

Publication number
JPS5725035A
JPS5725035A JP9874980A JP9874980A JPS5725035A JP S5725035 A JPS5725035 A JP S5725035A JP 9874980 A JP9874980 A JP 9874980A JP 9874980 A JP9874980 A JP 9874980A JP S5725035 A JPS5725035 A JP S5725035A
Authority
JP
Japan
Prior art keywords
register
signal
time division
data
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9874980A
Other languages
Japanese (ja)
Inventor
Yoshimasa Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9874980A priority Critical patent/JPS5725035A/en
Publication of JPS5725035A publication Critical patent/JPS5725035A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
  • Image Generation (AREA)

Abstract

PURPOSE:To simultaneously control plural display devices by a simple circuit configuration, by using in common one character generator by time division with a timing signal, providing a data register on the prestage of a dot register, and correcting a phase shift which is caused by time division. CONSTITUTION:By use of a signal which has been generated by a timing circuit 8, data of display memories A12, B13, C27 and D28 are read out by time division, and are set to a character address register 15. A data pattern of an address which has been designated by the register 15 of a character generator 17 is read out, is shifted by a phase difference portion according to a time division control, is set to character data registers A29, B30, C31 and D32, and after that, these contents are set simultaneously to dot registers A21, B22, C33 and D34. By the timing from the circuit 8, a control signal which has been generated by a display controlling signal circuit 10 is synthesized with a signal from the dot register by video signal circuits A23, B24, C35 and D36, and is sent to display devices A, B, C and D.
JP9874980A 1980-07-21 1980-07-21 Character display controller Pending JPS5725035A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9874980A JPS5725035A (en) 1980-07-21 1980-07-21 Character display controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9874980A JPS5725035A (en) 1980-07-21 1980-07-21 Character display controller

Publications (1)

Publication Number Publication Date
JPS5725035A true JPS5725035A (en) 1982-02-09

Family

ID=14228105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9874980A Pending JPS5725035A (en) 1980-07-21 1980-07-21 Character display controller

Country Status (1)

Country Link
JP (1) JPS5725035A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60252413A (en) * 1984-05-28 1985-12-13 Touri:Kk Preventive and remedy for disease of aquatic animal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60252413A (en) * 1984-05-28 1985-12-13 Touri:Kk Preventive and remedy for disease of aquatic animal

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