JPS5720993A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS5720993A
JPS5720993A JP9447680A JP9447680A JPS5720993A JP S5720993 A JPS5720993 A JP S5720993A JP 9447680 A JP9447680 A JP 9447680A JP 9447680 A JP9447680 A JP 9447680A JP S5720993 A JPS5720993 A JP S5720993A
Authority
JP
Japan
Prior art keywords
layer
layers
insulating film
high integration
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9447680A
Other languages
Japanese (ja)
Inventor
Naotake Tadama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9447680A priority Critical patent/JPS5720993A/en
Publication of JPS5720993A publication Critical patent/JPS5720993A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To achieve high integration and to improve reliability by arranging fuses on a semiconductor substrate with a prescribed difference in level and connecting respective fuse parts. CONSTITUTION:A polycrystal silicon layer having added impurities is divided into layers 17a and 17b; and one terminal of the layer 17a is connected to an n type semiconductor layer 14 and the layer 17b is wired opposite the layer 17a across an insulating film 18. Further, they are covered with an insulating film 20 and some part of the film 20 is opened for the wiring of bit lines 19, which are connected to the layer 17b. Thus, a fuse has double-layer structure consisting of the layers 17a and 17b arranged with a prescribed step, and consequently the two-dimensional size of the memory cell itself is reduced, enabling high integration.
JP9447680A 1980-07-10 1980-07-10 Semiconductor storage device Pending JPS5720993A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9447680A JPS5720993A (en) 1980-07-10 1980-07-10 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9447680A JPS5720993A (en) 1980-07-10 1980-07-10 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS5720993A true JPS5720993A (en) 1982-02-03

Family

ID=14111321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9447680A Pending JPS5720993A (en) 1980-07-10 1980-07-10 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS5720993A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4748490A (en) * 1985-08-01 1988-05-31 Texas Instruments Incorporated Deep polysilicon emitter antifuse memory cell
JPH01122451A (en) * 1987-11-06 1989-05-15 Seiko Instr & Electron Ltd Manufacture of thermal head

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4748490A (en) * 1985-08-01 1988-05-31 Texas Instruments Incorporated Deep polysilicon emitter antifuse memory cell
JPH01122451A (en) * 1987-11-06 1989-05-15 Seiko Instr & Electron Ltd Manufacture of thermal head

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