JPS5759388A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS5759388A
JPS5759388A JP55134552A JP13455280A JPS5759388A JP S5759388 A JPS5759388 A JP S5759388A JP 55134552 A JP55134552 A JP 55134552A JP 13455280 A JP13455280 A JP 13455280A JP S5759388 A JPS5759388 A JP S5759388A
Authority
JP
Japan
Prior art keywords
floating gate
insulating layer
layer
gate
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55134552A
Other languages
Japanese (ja)
Inventor
Kiyoshi Miyasaka
Mitsuo Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55134552A priority Critical patent/JPS5759388A/en
Publication of JPS5759388A publication Critical patent/JPS5759388A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To achieve high integration without decreasing writing efficiency, by embedding a floating gate in an insulating layer provided on a surface of a substrate, and inserting first and second control gates which are electrically connected via an insulating layer above and below the floating gate. CONSTITUTION:The floating gate 22 is embedded in the insulating layer 21 provided on the surface of the semiconductor substrate 20. The first and second control gates 23 and 24 which are electrically connected are inserted above and below the floating gate 22 via the insulating layer 21. For example, above the silicon dioxide insulating film 21 provided on the surface 201 of the P layer silicon substrate 20, three layers, i.e., the first polysilicon control gate 23, the floating gate layer 22 which is in an electrically floating state, and the second control gate layer 24 which is embedded below extended parts 221 at both ends and is connected with the first control gate 23 by a connecting means 25 are provided. In this constitution, high integration is achieved without decreasing writing efficiency.
JP55134552A 1980-09-27 1980-09-27 Semiconductor storage device Pending JPS5759388A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55134552A JPS5759388A (en) 1980-09-27 1980-09-27 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55134552A JPS5759388A (en) 1980-09-27 1980-09-27 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS5759388A true JPS5759388A (en) 1982-04-09

Family

ID=15130981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55134552A Pending JPS5759388A (en) 1980-09-27 1980-09-27 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS5759388A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01142179A (en) * 1987-11-30 1989-06-05 Furukawa Co Ltd Sky parking device
US5378910A (en) * 1992-07-08 1995-01-03 Kabushiki Kaisha Toshiba Memory transistor having increased interelectrode capacitance
JPH09199619A (en) * 1996-01-03 1997-07-31 Lg Semicon Co Ltd Nonvolatile memory device and its fabrication method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01142179A (en) * 1987-11-30 1989-06-05 Furukawa Co Ltd Sky parking device
US5378910A (en) * 1992-07-08 1995-01-03 Kabushiki Kaisha Toshiba Memory transistor having increased interelectrode capacitance
JPH09199619A (en) * 1996-01-03 1997-07-31 Lg Semicon Co Ltd Nonvolatile memory device and its fabrication method

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