JPS57204135A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57204135A
JPS57204135A JP8825581A JP8825581A JPS57204135A JP S57204135 A JPS57204135 A JP S57204135A JP 8825581 A JP8825581 A JP 8825581A JP 8825581 A JP8825581 A JP 8825581A JP S57204135 A JPS57204135 A JP S57204135A
Authority
JP
Japan
Prior art keywords
film
glass
flattened
thickness
field region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8825581A
Other languages
Japanese (ja)
Inventor
Akira Kurosawa
Sunao Shibata
Hisakazu Iizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8825581A priority Critical patent/JPS57204135A/en
Publication of JPS57204135A publication Critical patent/JPS57204135A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To flatten the surface of an element by a method wherein a thick insulating film is buried, a glass film is deposited onto the surface and melted and flattened, and the surface is etched uniformly in a BOX method burying the thick insulating film into a field region. CONSTITUTION:A P type Si substrate 1 is coated with a thermal oxide film 2 with thickness such as 500Angstrom one and an Al film 3 with thickness such as 0.5- 0.7mu one. A section functioning as the field region is removed while using a resist film 4 as a mask, and boron ions are implanted in the bottom of a concave section in order to prevent inversion. An SiO2 film 5 is deposited through a plasm CVD method. The SiO2 film 5 in the vicinity of difference in stages of the concave section is removed, and the resist film 4 is dissolved. The film 9 of phosphorus silicide glass or boron-phosphorus silicide glass is deposited onto the surface, and thermally treated at approximately 1,000 deg.C. Accordingly, when the surface of the glass film 9 is flattened and the surface is etched uniformly in a reactive gas atmosphere, the element with the flat surface is obtained.
JP8825581A 1981-06-10 1981-06-10 Manufacture of semiconductor device Pending JPS57204135A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8825581A JPS57204135A (en) 1981-06-10 1981-06-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8825581A JPS57204135A (en) 1981-06-10 1981-06-10 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57204135A true JPS57204135A (en) 1982-12-14

Family

ID=13937755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8825581A Pending JPS57204135A (en) 1981-06-10 1981-06-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57204135A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4679299A (en) * 1986-08-11 1987-07-14 Ncr Corporation Formation of self-aligned stacked CMOS structures by lift-off
US4764483A (en) * 1986-09-19 1988-08-16 Matsushita Electric Industrial Co., Ltd. Method for burying a step in a semiconductor substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5226182A (en) * 1975-08-25 1977-02-26 Hitachi Ltd Manufacturing method of semi-conductor unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5226182A (en) * 1975-08-25 1977-02-26 Hitachi Ltd Manufacturing method of semi-conductor unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4679299A (en) * 1986-08-11 1987-07-14 Ncr Corporation Formation of self-aligned stacked CMOS structures by lift-off
US4764483A (en) * 1986-09-19 1988-08-16 Matsushita Electric Industrial Co., Ltd. Method for burying a step in a semiconductor substrate

Similar Documents

Publication Publication Date Title
JPS57211267A (en) Semiconductor device and manufacture thereof
JPS57204135A (en) Manufacture of semiconductor device
JPS5659694A (en) Manufacture of thin film
JPS5795625A (en) Manufacture of semiconductor device
JPS57207377A (en) Manufacture of semiconductor device
JPS57204148A (en) Manufacture of semiconductor device
JPS5624937A (en) Manufacture of semiconductor device
JPS57164546A (en) Semiconductor device
JPS56130940A (en) Manufacture of semiconductor device
JPS5632768A (en) Semiconductor device
JPS6455865A (en) Manufacture of semiconductor device
JPS5627936A (en) Semiconductor device and manufacture thereof
JPS5618419A (en) Manufacture of semiconductor device
JPS54124687A (en) Production of semiconductor device
JPS57124477A (en) Manufacture of semiconductor device
JPS57180144A (en) Manufacture of semiconductor device
JPS56146254A (en) Manufacture of semiconductor device
JPS57207372A (en) Manufacture of metal oxide semiconductor integrated circuit device
JPS5650579A (en) Manufacture of junction type field effect semiconductor device
JPS5693315A (en) Manufacture of semiconductor device
JPS57186341A (en) Semiconductor device
JPS57193063A (en) Manufacture of semiconductor device
JPS57180165A (en) Semiconductor device and manufacture thereof
JPS55134932A (en) Preparation of semiconductor device
JPS6455846A (en) Semiconductor device