JPS57203136A - High speed processor for data with label - Google Patents

High speed processor for data with label

Info

Publication number
JPS57203136A
JPS57203136A JP8851281A JP8851281A JPS57203136A JP S57203136 A JPS57203136 A JP S57203136A JP 8851281 A JP8851281 A JP 8851281A JP 8851281 A JP8851281 A JP 8851281A JP S57203136 A JPS57203136 A JP S57203136A
Authority
JP
Japan
Prior art keywords
data
label
stored
high speed
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8851281A
Other languages
Japanese (ja)
Inventor
Yoshio Suemitsu
Morio Asano
Toshiyuki Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8851281A priority Critical patent/JPS57203136A/en
Publication of JPS57203136A publication Critical patent/JPS57203136A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To perform label discrimination at a high speed by string an RAM with data which correspond to labels for the trnsfer of labeled.
CONSTITUTION: Labeled data are inputted to a signal input 1; the label data of the data are stored in an RAM address counter 2 through a label line 6, and the data are stored in an RAM data register 3 through a data line 7. Then, the contents of the register 3 are stored in an address of an RAM4 specified by the counter 2 through a data information line 9. All of the data stored in the RAM4 are inputted to an external data processor at a high speed by an interface circuit 5. The data inputted to the data processor are already edited corresponding to the label, so they are used without label discrimination.
COPYRIGHT: (C)1982,JPO&Japio
JP8851281A 1981-06-09 1981-06-09 High speed processor for data with label Pending JPS57203136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8851281A JPS57203136A (en) 1981-06-09 1981-06-09 High speed processor for data with label

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8851281A JPS57203136A (en) 1981-06-09 1981-06-09 High speed processor for data with label

Publications (1)

Publication Number Publication Date
JPS57203136A true JPS57203136A (en) 1982-12-13

Family

ID=13944871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8851281A Pending JPS57203136A (en) 1981-06-09 1981-06-09 High speed processor for data with label

Country Status (1)

Country Link
JP (1) JPS57203136A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3920683A1 (en) * 1989-06-19 1991-01-10 Musashi Seimitsu Kogyo Kk BALL JOINT ARRANGEMENT

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5477042A (en) * 1977-12-02 1979-06-20 Hitachi Ltd Data switching input equipment

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5477042A (en) * 1977-12-02 1979-06-20 Hitachi Ltd Data switching input equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3920683A1 (en) * 1989-06-19 1991-01-10 Musashi Seimitsu Kogyo Kk BALL JOINT ARRANGEMENT
DE3920683C2 (en) * 1989-06-19 1998-05-28 Musashi Seimitsu Kogyo Kk Ball joint arrangement

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