JPS5719854A - History storing system - Google Patents
History storing systemInfo
- Publication number
- JPS5719854A JPS5719854A JP9343080A JP9343080A JPS5719854A JP S5719854 A JPS5719854 A JP S5719854A JP 9343080 A JP9343080 A JP 9343080A JP 9343080 A JP9343080 A JP 9343080A JP S5719854 A JPS5719854 A JP S5719854A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- address
- memory
- microinstruction
- history
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To suppress the fact that information in a history storing circuit becomes only a redundant address information by a loop, etc., by suppressing a registration by a history registration controlling circuit, in case when a specific pattern contained in a microinstruction word has been detected. CONSTITUTION:When an address information S1 from an address instructing circuit 4 is address alpha, a microinstruction (a) is read out as a microinstruction word S2 from a microinstruction word memory 3, and the address alpha is registered in a history circuit 2. Subsequently, address beta1 from the circuit 4 is sent to the memory 3 as the address information S1, and a microinstruction b1 is read out from the memory 3. In this case, since an inhibit instruction signal S4 is not outputted from a history registration inhibiting and holding circuit 7, and the address beta1 of the instruction b1 is stored in the circuit 2. Subsequently, when an address beta2 is supplied to the memory 3 from the circuit 4, an instruction b2 is read out, a pattern detection signal S3 is outputted from a specific pattern detecting circuit 5, the signal S4 is outputted from the circuit 7, and it is inhibited to register the address beta2 to the circuit 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9343080A JPS5719854A (en) | 1980-07-09 | 1980-07-09 | History storing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9343080A JPS5719854A (en) | 1980-07-09 | 1980-07-09 | History storing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5719854A true JPS5719854A (en) | 1982-02-02 |
Family
ID=14082085
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9343080A Pending JPS5719854A (en) | 1980-07-09 | 1980-07-09 | History storing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5719854A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02260117A (en) * | 1989-03-30 | 1990-10-22 | Konica Corp | Magnetic recording medium |
-
1980
- 1980-07-09 JP JP9343080A patent/JPS5719854A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02260117A (en) * | 1989-03-30 | 1990-10-22 | Konica Corp | Magnetic recording medium |
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