JPS57130153A - Program control device - Google Patents
Program control deviceInfo
- Publication number
- JPS57130153A JPS57130153A JP1527681A JP1527681A JPS57130153A JP S57130153 A JPS57130153 A JP S57130153A JP 1527681 A JP1527681 A JP 1527681A JP 1527681 A JP1527681 A JP 1527681A JP S57130153 A JPS57130153 A JP S57130153A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- control
- register
- address
- effectiveness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Detection And Correction Of Errors (AREA)
- Safety Devices In Control Systems (AREA)
Abstract
PURPOSE:To prevent malfunctions of a program control device, by adding a code ensuring effectiveness to control information of the program control device. CONSTITUTION:When the initial value of a storage address register 12 is given to a control storage device 14, an instruction corresponding to the address is read out and is inputted to an instruction register 8. The effectiveness code in the instruction register 8 is sent to an effectiveness code detecting circuit 9 through a signal line (c), and it is confirmed that the instruction is effective as control information. Only when it is confirmed that the parity is correct and that the instruction is effective in a parity checking circuit 10 and the effectiveness code detecting circuit 9 respectively, the control corresponding to control information inputted to a decoder 11 is executed. Simultaneously, contents of the address field in the instruction register 8 are inputted to the storage address register 12, and the instruction stored in this address is next read out from the control storage device 14. Thus, the program control is executed sequentially.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1527681A JPS57130153A (en) | 1981-02-04 | 1981-02-04 | Program control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1527681A JPS57130153A (en) | 1981-02-04 | 1981-02-04 | Program control device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57130153A true JPS57130153A (en) | 1982-08-12 |
Family
ID=11884331
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1527681A Pending JPS57130153A (en) | 1981-02-04 | 1981-02-04 | Program control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57130153A (en) |
-
1981
- 1981-02-04 JP JP1527681A patent/JPS57130153A/en active Pending
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