JPS57192138A - Logical circuit providing power save function - Google Patents

Logical circuit providing power save function

Info

Publication number
JPS57192138A
JPS57192138A JP56077169A JP7716981A JPS57192138A JP S57192138 A JPS57192138 A JP S57192138A JP 56077169 A JP56077169 A JP 56077169A JP 7716981 A JP7716981 A JP 7716981A JP S57192138 A JPS57192138 A JP S57192138A
Authority
JP
Japan
Prior art keywords
logical circuit
trq4
trs
series
power consumption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56077169A
Other languages
Japanese (ja)
Inventor
Toshitaka Tsuda
Shigenori Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56077169A priority Critical patent/JPS57192138A/en
Publication of JPS57192138A publication Critical patent/JPS57192138A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce power consumption, to control heat generation and to increase the performance of a device, by connecting a means controlling transistors not to flow currents when a disabling signal is inputted to an input, in series with the transistors one end of which is grounded. CONSTITUTION:Transistors (TRs) Q1 and Q2 are connected in series, one end of the TRs Q1 and Q2 is grounded, and a control TRQ4 is inserted between the TRs Q1 and Q2 and a load TRQ3 to constitute an NAND logical circuit. Inputs A and B are respectively inputted to the TRs Q1 and Q2 of the logical circuit and a disabling signal DS is applied to the TRQ4. The TRQ4 is turned off by zeroing the signal DS when the logical circuit is not in use to make an output C to always 1 independently of the state of the inputs A and B, allowing to reduce the power consumption at not in use. The controlling TRQ4 is connected in series with an NOR logical circuit in parallel connection of the TRs Q1 and Q2. The signal DS is applied to the TRQ4 to reduce power consumption similarly as in the case of the NAND circuit.
JP56077169A 1981-05-21 1981-05-21 Logical circuit providing power save function Pending JPS57192138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56077169A JPS57192138A (en) 1981-05-21 1981-05-21 Logical circuit providing power save function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56077169A JPS57192138A (en) 1981-05-21 1981-05-21 Logical circuit providing power save function

Publications (1)

Publication Number Publication Date
JPS57192138A true JPS57192138A (en) 1982-11-26

Family

ID=13626282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56077169A Pending JPS57192138A (en) 1981-05-21 1981-05-21 Logical circuit providing power save function

Country Status (1)

Country Link
JP (1) JPS57192138A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0493293A2 (en) * 1990-12-26 1992-07-01 International Business Machines Corporation Bipolar element bifet array decoder
DE19905749B4 (en) * 1998-02-12 2004-04-29 LG Semicon Co., Ltd., Cheongju Standby circuit with reduced power consumption

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5531357A (en) * 1978-08-28 1980-03-05 Nec Corp Insulated gate type field effect transistor logic gate circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5531357A (en) * 1978-08-28 1980-03-05 Nec Corp Insulated gate type field effect transistor logic gate circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0493293A2 (en) * 1990-12-26 1992-07-01 International Business Machines Corporation Bipolar element bifet array decoder
DE19905749B4 (en) * 1998-02-12 2004-04-29 LG Semicon Co., Ltd., Cheongju Standby circuit with reduced power consumption

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