JPS57192110A - Muting circuit - Google Patents
Muting circuitInfo
- Publication number
- JPS57192110A JPS57192110A JP56076470A JP7647081A JPS57192110A JP S57192110 A JPS57192110 A JP S57192110A JP 56076470 A JP56076470 A JP 56076470A JP 7647081 A JP7647081 A JP 7647081A JP S57192110 A JPS57192110 A JP S57192110A
- Authority
- JP
- Japan
- Prior art keywords
- turns
- trq
- amplifier
- amp2
- pop noise
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
- Amplifiers (AREA)
Abstract
PURPOSE: To suppress the pop noise of an amplifier and to enable to set the leading time of the amplifier freely, by providing a Schmitt circuit which turns off a signal transmitting path of the amplifier and a time constant circuit.
CONSTITUTION: When a power supply ± Vcc is applied, a transistor (TR)Q12 turns on, and a TRO13 turns on with a voltage produced for a diode D1 and a contact (a) between stages of amplifiers Amp1 and Amp2 is opened. Thus, a floating potential can be applied to the input of the amplifier Amp2, muting can be given and pop noise can be suppressed. Further, since a capacitor C11is charged with a time constant of R12×C11, a TRQ11 turns on. With the TRQ11 turned on, the TRQ12 turns off. Thus, the TRQ13 turns off and the contact (a) is closed and the amplifiers Amp1 and Amp2 start operation, allowing to suppress the production of pop noise.
COPYRIGHT: (C)1982,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56076470A JPS57192110A (en) | 1981-05-22 | 1981-05-22 | Muting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56076470A JPS57192110A (en) | 1981-05-22 | 1981-05-22 | Muting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57192110A true JPS57192110A (en) | 1982-11-26 |
Family
ID=13606053
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56076470A Pending JPS57192110A (en) | 1981-05-22 | 1981-05-22 | Muting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57192110A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61144905A (en) * | 1984-12-17 | 1986-07-02 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | Sprious signal reducing circuit |
US5255094A (en) * | 1990-10-10 | 1993-10-19 | Thomson Consumer Electronics, S.A. | Muting circuit for eliminating transient signals generated due to power supply turn-on and turn-off |
US20230318588A1 (en) * | 2022-03-31 | 2023-10-05 | Texas Instruments Incorporated | Signal chatter mitigation |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS541350B2 (en) * | 1976-03-22 | 1979-01-23 |
-
1981
- 1981-05-22 JP JP56076470A patent/JPS57192110A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS541350B2 (en) * | 1976-03-22 | 1979-01-23 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61144905A (en) * | 1984-12-17 | 1986-07-02 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | Sprious signal reducing circuit |
JPH0620167B2 (en) * | 1984-12-17 | 1994-03-16 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | Spurious signal reduction circuit |
US5255094A (en) * | 1990-10-10 | 1993-10-19 | Thomson Consumer Electronics, S.A. | Muting circuit for eliminating transient signals generated due to power supply turn-on and turn-off |
US20230318588A1 (en) * | 2022-03-31 | 2023-10-05 | Texas Instruments Incorporated | Signal chatter mitigation |
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