JPS5621071A - Signal level indicator - Google Patents

Signal level indicator

Info

Publication number
JPS5621071A
JPS5621071A JP9676679A JP9676679A JPS5621071A JP S5621071 A JPS5621071 A JP S5621071A JP 9676679 A JP9676679 A JP 9676679A JP 9676679 A JP9676679 A JP 9676679A JP S5621071 A JPS5621071 A JP S5621071A
Authority
JP
Japan
Prior art keywords
voltage
capacitor
level indicator
rectified
charges
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9676679A
Other languages
Japanese (ja)
Inventor
Hiroshi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP9676679A priority Critical patent/JPS5621071A/en
Publication of JPS5621071A publication Critical patent/JPS5621071A/en
Pending legal-status Critical Current

Links

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  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE: To make reading of a level indicator easier by appropriately controlling a field-effect transistor connected in parallel with a capacitor whose voltage is indicated by the level indicator.
CONSTITUTION: The signal voltage of a signal source 1 is rectified by a diode 5 and charges a capacitor C1 with a positive voltage, the voltage of the capacitor C1 is amplified by a DC amplifier 3 and then applied to a level indicator 4, and the level of the input signal is indicated. On the other hand, the voltage of the input signal is rectified by a diode 6 in reverse direction and charges a capacitor C2, and the voltage of the charged capacitor C2 is adjusted to an appropriate value with a variable resistor 8 and applied to the gate of a field-effect transistor 7 as a control voltage.
COPYRIGHT: (C)1981,JPO&Japio
JP9676679A 1979-07-31 1979-07-31 Signal level indicator Pending JPS5621071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9676679A JPS5621071A (en) 1979-07-31 1979-07-31 Signal level indicator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9676679A JPS5621071A (en) 1979-07-31 1979-07-31 Signal level indicator

Publications (1)

Publication Number Publication Date
JPS5621071A true JPS5621071A (en) 1981-02-27

Family

ID=14173749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9676679A Pending JPS5621071A (en) 1979-07-31 1979-07-31 Signal level indicator

Country Status (1)

Country Link
JP (1) JPS5621071A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014071674A1 (en) * 2012-11-09 2014-05-15 联合汽车电子有限公司 Direct-current isolation buck convertor and bus voltage detection circuit thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014071674A1 (en) * 2012-11-09 2014-05-15 联合汽车电子有限公司 Direct-current isolation buck convertor and bus voltage detection circuit thereof

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