JPS57190352A - Programmable read only memory - Google Patents
Programmable read only memoryInfo
- Publication number
- JPS57190352A JPS57190352A JP7590481A JP7590481A JPS57190352A JP S57190352 A JPS57190352 A JP S57190352A JP 7590481 A JP7590481 A JP 7590481A JP 7590481 A JP7590481 A JP 7590481A JP S57190352 A JPS57190352 A JP S57190352A
- Authority
- JP
- Japan
- Prior art keywords
- read
- write
- substrate voltage
- enhance
- generating circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
PURPOSE:To contrive to enhance read/write characteristic at a channel injection type programmable read only memory (PROM) by a method wherein a substrate voltage generating circuit and a control circuit for change-over of substrate voltage when read/write is to be performed are made as built-in. CONSTITUTION:Because channel length is selected as not to deteriorate the traditional write characteristic, the read speed is sacrificed ultimately. The substrate voltage generating circuit and the control circut for change-over of the substrate voltage when read/write is to be performed are made as built-in, channel length of the memory cell is shortened to improve gm, the discharging speed of electric charge of a digit line is made fast to enhance the read speed, and in regard to write, a reverse bias is applied to the substrate making the substrate voltage generating circuit to operate, and a leakage current of the memory cell is suppressed to enhance the write characteristic. At the exemplified UV-PROM, when write is performed with the reverse bias VSUB=-3V, the margin for electric power source voltage is enlarged, and when read is to be performed, the substrate voltage becomes as VSUB=0, and the high speed property can be obtained.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7590481A JPS57190352A (en) | 1981-05-20 | 1981-05-20 | Programmable read only memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7590481A JPS57190352A (en) | 1981-05-20 | 1981-05-20 | Programmable read only memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57190352A true JPS57190352A (en) | 1982-11-22 |
Family
ID=13589783
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7590481A Pending JPS57190352A (en) | 1981-05-20 | 1981-05-20 | Programmable read only memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57190352A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0322002A2 (en) * | 1987-12-01 | 1989-06-28 | STMicroelectronics S.r.l. | Voltage supply switching device for nonvolatile memories in MOS technology |
JPH01253264A (en) * | 1988-03-31 | 1989-10-09 | Sharp Corp | Semiconductor integrated circuit |
-
1981
- 1981-05-20 JP JP7590481A patent/JPS57190352A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0322002A2 (en) * | 1987-12-01 | 1989-06-28 | STMicroelectronics S.r.l. | Voltage supply switching device for nonvolatile memories in MOS technology |
JPH01253264A (en) * | 1988-03-31 | 1989-10-09 | Sharp Corp | Semiconductor integrated circuit |
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