JPS57186323A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57186323A
JPS57186323A JP7042581A JP7042581A JPS57186323A JP S57186323 A JPS57186323 A JP S57186323A JP 7042581 A JP7042581 A JP 7042581A JP 7042581 A JP7042581 A JP 7042581A JP S57186323 A JPS57186323 A JP S57186323A
Authority
JP
Japan
Prior art keywords
layer
groove
electrode
hole
polycrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7042581A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP7042581A priority Critical patent/JPS57186323A/en
Publication of JPS57186323A publication Critical patent/JPS57186323A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To be adapted for the formation of a drawing electrode of a low resistance by forming by etching a groove on the surface of a semiconductor substrate, burying the groove with a polycrystalline semiconductor layer, introducing a conductive type deciding impurity to the groove, thereby facilitating the formation of a diffused layer having a narrow width and a high depth. CONSTITUTION:A dielectric film 12 is covered on the surface of a P-type Si substrate 11, a window is opened by photoetching, and a hole of approx. 0.5mum of width and approx. 2mum of depth is opened by anisotropic etching with ion etching or KOH solution. Then, a polycrystalline Si layer 13 containing an N type impurity such as As, P or the like is accumulated by a CVD method on the overall surface including the hole, or a polycrystalline Si layer 13 containing no impurity is accumulated, and N-type impurity ions are then implanted. In this manner, the layer 13 buried in the hole is used as an electrode contacted with the prescribed region under the layer 13, and the layer 13 on the film 12 connected to th electrode is used as a drawing electrode.
JP7042581A 1981-05-11 1981-05-11 Semiconductor device Pending JPS57186323A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7042581A JPS57186323A (en) 1981-05-11 1981-05-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7042581A JPS57186323A (en) 1981-05-11 1981-05-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57186323A true JPS57186323A (en) 1982-11-16

Family

ID=13431105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7042581A Pending JPS57186323A (en) 1981-05-11 1981-05-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57186323A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03218626A (en) * 1989-11-14 1991-09-26 Mitsubishi Electric Corp Wiring contact structure of semiconductor device and manufacture thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010578A (en) * 1973-05-24 1975-02-03

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010578A (en) * 1973-05-24 1975-02-03

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03218626A (en) * 1989-11-14 1991-09-26 Mitsubishi Electric Corp Wiring contact structure of semiconductor device and manufacture thereof

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