JPS57182860A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS57182860A
JPS57182860A JP56067814A JP6781481A JPS57182860A JP S57182860 A JPS57182860 A JP S57182860A JP 56067814 A JP56067814 A JP 56067814A JP 6781481 A JP6781481 A JP 6781481A JP S57182860 A JPS57182860 A JP S57182860A
Authority
JP
Japan
Prior art keywords
fault
access
data processing
circuit
stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56067814A
Other languages
Japanese (ja)
Inventor
Kazuhiro Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56067814A priority Critical patent/JPS57182860A/en
Publication of JPS57182860A publication Critical patent/JPS57182860A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To grasp easily the cause of a fault, by providing an access stack in a data processing device and recording contents of the access stack to a predetermined fixed address area of a storage device when a fault occurs. CONSTITUTION:Each time a memory access controlling circuit 3 performs the memory access operation to a storage device 2, an access stack 9 can store the value of the address and contents of the request. If a fault occurs in a data processing device 1, an error detecting circuit 8 is operated to report the fault to a data processing/controlling circuit 7. The circuit 7 reads out access information from the access stack 9 to store it in a fault storage area 10 in parallel with the execution of the fault processing. In this case, the circuit 7 gives priority to access information in respect to the order of this fault recording so that contents of the access stack 9 for the fault recording to the storage device 2 through the controlling circuit 3 are not destructed similarly to the execution of a program.
JP56067814A 1981-05-06 1981-05-06 Data processing device Pending JPS57182860A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56067814A JPS57182860A (en) 1981-05-06 1981-05-06 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56067814A JPS57182860A (en) 1981-05-06 1981-05-06 Data processing device

Publications (1)

Publication Number Publication Date
JPS57182860A true JPS57182860A (en) 1982-11-10

Family

ID=13355783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56067814A Pending JPS57182860A (en) 1981-05-06 1981-05-06 Data processing device

Country Status (1)

Country Link
JP (1) JPS57182860A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59189458A (en) * 1983-04-13 1984-10-27 Fujitsu Ltd Ras information managing system
JPS59229658A (en) * 1983-06-10 1984-12-24 Nec Corp Information processor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4966253A (en) * 1972-10-31 1974-06-27
JPS4985939A (en) * 1972-12-22 1974-08-17
JPS53109454A (en) * 1977-03-07 1978-09-25 Nec Corp Logical condition follower

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4966253A (en) * 1972-10-31 1974-06-27
JPS4985939A (en) * 1972-12-22 1974-08-17
JPS53109454A (en) * 1977-03-07 1978-09-25 Nec Corp Logical condition follower

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59189458A (en) * 1983-04-13 1984-10-27 Fujitsu Ltd Ras information managing system
JPS59229658A (en) * 1983-06-10 1984-12-24 Nec Corp Information processor

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