JPS57177530A - Processing of semiconductor wafer - Google Patents

Processing of semiconductor wafer

Info

Publication number
JPS57177530A
JPS57177530A JP6246181A JP6246181A JPS57177530A JP S57177530 A JPS57177530 A JP S57177530A JP 6246181 A JP6246181 A JP 6246181A JP 6246181 A JP6246181 A JP 6246181A JP S57177530 A JPS57177530 A JP S57177530A
Authority
JP
Japan
Prior art keywords
wafer
crystal defect
constitution
damage
defect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6246181A
Other languages
Japanese (ja)
Inventor
Takaaki Aoshima
Akira Yoshinaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6246181A priority Critical patent/JPS57177530A/en
Publication of JPS57177530A publication Critical patent/JPS57177530A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To properly control the generation of a crystal defect at the deepest part of the wafer by a method wherein a heat treatment is performed after damage has been given on the surface of the wafer from outside. CONSTITUTION:When the damage 2 has been formed on the surface layer by irradiating an ion beam on the element forming surface alone of an Si wafer 1 and a thermal oxide film 3 has been formed, the excessive defect 2 on the surface layer is diffused into the interior and a crystal defect 4 is formed. Subsequently, an FET is formed using the method commonly in use. According to this constitution, the wafer can be formed properly by controlling the crystal defect in the deep part of the wafer, the detrimental impurities and the crystal defects are gathered from the active region where a semiconductor element will be formed, and at the same time, the plastic deformation of the wafer due to the thermal stress generated while a heat treatment is performed can be prevented without fail.
JP6246181A 1981-04-27 1981-04-27 Processing of semiconductor wafer Pending JPS57177530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6246181A JPS57177530A (en) 1981-04-27 1981-04-27 Processing of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6246181A JPS57177530A (en) 1981-04-27 1981-04-27 Processing of semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS57177530A true JPS57177530A (en) 1982-11-01

Family

ID=13200861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6246181A Pending JPS57177530A (en) 1981-04-27 1981-04-27 Processing of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS57177530A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4885257A (en) * 1983-07-29 1989-12-05 Kabushiki Kaisha Toshiba Gettering process with multi-step annealing and inert ion implantation
US5098852A (en) * 1989-07-05 1992-03-24 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device by mega-electron volt ion implantation
US5635414A (en) * 1995-03-28 1997-06-03 Zakaluk; Gregory Low cost method of fabricating shallow junction, Schottky semiconductor devices
JP2015023039A (en) * 2013-07-16 2015-02-02 住友重機械工業株式会社 Method and apparatus of manufacturing semiconductor device
JP2015095534A (en) * 2013-11-12 2015-05-18 住友重機械工業株式会社 Method for manufacturing semiconductor device and device for manufacturing semiconductor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4885257A (en) * 1983-07-29 1989-12-05 Kabushiki Kaisha Toshiba Gettering process with multi-step annealing and inert ion implantation
US5098852A (en) * 1989-07-05 1992-03-24 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device by mega-electron volt ion implantation
US5635414A (en) * 1995-03-28 1997-06-03 Zakaluk; Gregory Low cost method of fabricating shallow junction, Schottky semiconductor devices
JP2015023039A (en) * 2013-07-16 2015-02-02 住友重機械工業株式会社 Method and apparatus of manufacturing semiconductor device
JP2015095534A (en) * 2013-11-12 2015-05-18 住友重機械工業株式会社 Method for manufacturing semiconductor device and device for manufacturing semiconductor

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