JPS57176590A - Memory device - Google Patents

Memory device

Info

Publication number
JPS57176590A
JPS57176590A JP56059175A JP5917581A JPS57176590A JP S57176590 A JPS57176590 A JP S57176590A JP 56059175 A JP56059175 A JP 56059175A JP 5917581 A JP5917581 A JP 5917581A JP S57176590 A JPS57176590 A JP S57176590A
Authority
JP
Japan
Prior art keywords
word line
decoder
constitution
mos transistor
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56059175A
Other languages
Japanese (ja)
Inventor
Satoshi Umeki
Tsuguhiro Matsuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP56059175A priority Critical patent/JPS57176590A/en
Publication of JPS57176590A publication Critical patent/JPS57176590A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To assure a suitable address function over all address lines, without increasing capacity of a decoder, by providing an MOS transistor on the way of row or column address lines. CONSTITUTION:An NOR type address decoder 2 is connected to one end of a word line 1, which is connected with a plurality of bit lines. A signal level control means 5 is provided on the way of the word line 1. In this means 5, an MOS transistor is used, and the gate and the source are connected to the word line 1 and the drain is connected to a power supply. With this constitution, even if the word line 1 is long or a voltage drop along the word line 1 is large, the means 5 can recover the signal voltage level. Thus, the signal level more than a prescribed value along the word line 1 can be assured without increasing the capacity of the decoder 2.
JP56059175A 1981-04-21 1981-04-21 Memory device Pending JPS57176590A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56059175A JPS57176590A (en) 1981-04-21 1981-04-21 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56059175A JPS57176590A (en) 1981-04-21 1981-04-21 Memory device

Publications (1)

Publication Number Publication Date
JPS57176590A true JPS57176590A (en) 1982-10-29

Family

ID=13105787

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56059175A Pending JPS57176590A (en) 1981-04-21 1981-04-21 Memory device

Country Status (1)

Country Link
JP (1) JPS57176590A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59174023A (en) * 1983-03-24 1984-10-02 Toshiba Corp Very large scale integrated circuit
EP0130793A2 (en) * 1983-06-29 1985-01-09 Fujitsu Limited Semiconductor memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59174023A (en) * 1983-03-24 1984-10-02 Toshiba Corp Very large scale integrated circuit
EP0130793A2 (en) * 1983-06-29 1985-01-09 Fujitsu Limited Semiconductor memory device
US4747083A (en) * 1983-06-29 1988-05-24 Fujitsu Limited Semiconductor memory with segmented word lines

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