JPS57170525A - Positioning control system for alignment stage - Google Patents

Positioning control system for alignment stage

Info

Publication number
JPS57170525A
JPS57170525A JP56055029A JP5502981A JPS57170525A JP S57170525 A JPS57170525 A JP S57170525A JP 56055029 A JP56055029 A JP 56055029A JP 5502981 A JP5502981 A JP 5502981A JP S57170525 A JPS57170525 A JP S57170525A
Authority
JP
Japan
Prior art keywords
output
counter
stage
fed
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56055029A
Other languages
Japanese (ja)
Inventor
Kazuo Minowa
Kimikichi Deguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56055029A priority Critical patent/JPS57170525A/en
Publication of JPS57170525A publication Critical patent/JPS57170525A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To position an alignment stage at a high speed in a high accuracy in an exposure device for transferring an IC pattern by performing both the speed control of the acceleration or deceleration at 1/2 of the moving distance of one step of the state as a vertex and the position control in the region of the vicinity of a target position. CONSTITUTION:A stage target positioning value X0, stage position information XR and a set signal phi1 are imputted to a counter 10, and the output of the counter is applied directly or through a date holer 11 to an absolute value detector 12. Then, this output is fed to an OR circuit 13 together with a start signal phi2, the output of the OR circuit is applied through a binary counter 14 to a differential amplifier 15, and this output is supplied through an integrator 16 to an inverting amplifier 17. On the other hand, the output of the counter 10 is branched, is then applied to an absolute value detector 21, the output of the detector is fed through an FF22 to the counter 14, the output of the counter 10 is further branched and is applied to a D/A converter 23. Differential amplifiers 18, 19 are provided between the output sid and an inverter 17, the output of an amplifier 19 is fed to a drive amplifier 20, and the stage is moved and positioned.
JP56055029A 1981-04-14 1981-04-14 Positioning control system for alignment stage Pending JPS57170525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56055029A JPS57170525A (en) 1981-04-14 1981-04-14 Positioning control system for alignment stage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56055029A JPS57170525A (en) 1981-04-14 1981-04-14 Positioning control system for alignment stage

Publications (1)

Publication Number Publication Date
JPS57170525A true JPS57170525A (en) 1982-10-20

Family

ID=12987235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56055029A Pending JPS57170525A (en) 1981-04-14 1981-04-14 Positioning control system for alignment stage

Country Status (1)

Country Link
JP (1) JPS57170525A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4893883A (en) * 1972-02-18 1973-12-04
JPS55102009A (en) * 1979-01-19 1980-08-04 Yaskawa Electric Mfg Co Ltd Deceleration instructing method in positioning control

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4893883A (en) * 1972-02-18 1973-12-04
JPS55102009A (en) * 1979-01-19 1980-08-04 Yaskawa Electric Mfg Co Ltd Deceleration instructing method in positioning control

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