JPS57169860A - Address testing equipment - Google Patents

Address testing equipment

Info

Publication number
JPS57169860A
JPS57169860A JP56053825A JP5382581A JPS57169860A JP S57169860 A JPS57169860 A JP S57169860A JP 56053825 A JP56053825 A JP 56053825A JP 5382581 A JP5382581 A JP 5382581A JP S57169860 A JPS57169860 A JP S57169860A
Authority
JP
Japan
Prior art keywords
input terminal
processor cpu
coinc
flip
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56053825A
Other languages
Japanese (ja)
Inventor
Osatoshi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Yokogawa Hokushin Electric Corp
Yokogawa Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp, Yokogawa Hokushin Electric Corp, Yokogawa Electric Works Ltd filed Critical Yokogawa Electric Corp
Priority to JP56053825A priority Critical patent/JPS57169860A/en
Publication of JPS57169860A publication Critical patent/JPS57169860A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To set an optional large number of addresses to be tested at a time by storing a random access memory with pointers corresponding to the addresses of a program memory to be tested, and then reporting read pointers to a processor. CONSTITUTION:A selector control signal TRAC, the read data RAMD of a random access memory PRAM, and a stobe signal STROBE outputted from a processor CPU are ANDed by an AND gate G2, whose output is supplied to the set input terminal of a flip-flop circuit FF. An output from the Q terminal of the flip-flop circuit FF is supplied to the forcible input terminal COINC of the processor CPU. The fordible input terminal COINC is an input terminal for signals for forcibly stopping, interrupting, and resetting the processor CPU, and its number depends upon the kind of forcing operation.
JP56053825A 1981-04-10 1981-04-10 Address testing equipment Pending JPS57169860A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56053825A JPS57169860A (en) 1981-04-10 1981-04-10 Address testing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56053825A JPS57169860A (en) 1981-04-10 1981-04-10 Address testing equipment

Publications (1)

Publication Number Publication Date
JPS57169860A true JPS57169860A (en) 1982-10-19

Family

ID=12953562

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56053825A Pending JPS57169860A (en) 1981-04-10 1981-04-10 Address testing equipment

Country Status (1)

Country Link
JP (1) JPS57169860A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59153247A (en) * 1983-02-18 1984-09-01 Omron Tateisi Electronics Co Debugging device
JPS6123253A (en) * 1984-07-11 1986-01-31 Hitachi Ltd Data processing system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54161859A (en) * 1978-06-13 1979-12-21 Nippon Telegr & Teleph Corp <Ntt> Program indexing system
JPS5582359A (en) * 1978-12-18 1980-06-21 Toshiba Corp Microprogram test unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54161859A (en) * 1978-06-13 1979-12-21 Nippon Telegr & Teleph Corp <Ntt> Program indexing system
JPS5582359A (en) * 1978-12-18 1980-06-21 Toshiba Corp Microprogram test unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59153247A (en) * 1983-02-18 1984-09-01 Omron Tateisi Electronics Co Debugging device
JPS6123253A (en) * 1984-07-11 1986-01-31 Hitachi Ltd Data processing system

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