JPS57160240A - Error controller - Google Patents

Error controller

Info

Publication number
JPS57160240A
JPS57160240A JP56046862A JP4686281A JPS57160240A JP S57160240 A JPS57160240 A JP S57160240A JP 56046862 A JP56046862 A JP 56046862A JP 4686281 A JP4686281 A JP 4686281A JP S57160240 A JPS57160240 A JP S57160240A
Authority
JP
Japan
Prior art keywords
error
circuit
signal
code
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56046862A
Other languages
Japanese (ja)
Inventor
Moichi Hirasawa
Akira Horiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56046862A priority Critical patent/JPS57160240A/en
Publication of JPS57160240A publication Critical patent/JPS57160240A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To minimize transmission efficiency while holding the possibility of error overlooking within a prescribed range by estimating the error rate of a communication path, and setting it to the adequate number of corrected errors. CONSTITUTION:A received code 8 is converted by a receiving buffer 11 in bit- parallel and stored and its output is supplied to an error correcting circuit 12 to detect an error pattern to be corrected, which is sent to a buffer 13 for error pattern and a shift register 15. The output of the buffer 13 is supplied to an error bit counting circuit 14 to calculate the number of error bits, thereby outputting a signal 20 or 21 in accordance with the count value. The register 15 stores information on whether a prescribed number of past words outputed by the circuit 12 have a code error or not successively; and the number of words having code errors in the stored information is made by a deciding circuit 16 into threshold value information and when the number is below a prescribed value, the signal 22 is held at a 1. In response to an AND signal 23 of the signal 22 and the output of the circuit 14, a decoded code word synthesizing circuit 24 adds the outputs of the buffers 11 and 13 to output a corrected code 25. When the decision result of the circuit 16 is above the prescribed value, the transmitted signal 9 of an ARQ is outputted.
JP56046862A 1981-03-27 1981-03-27 Error controller Pending JPS57160240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56046862A JPS57160240A (en) 1981-03-27 1981-03-27 Error controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56046862A JPS57160240A (en) 1981-03-27 1981-03-27 Error controller

Publications (1)

Publication Number Publication Date
JPS57160240A true JPS57160240A (en) 1982-10-02

Family

ID=12759139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56046862A Pending JPS57160240A (en) 1981-03-27 1981-03-27 Error controller

Country Status (1)

Country Link
JP (1) JPS57160240A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2599532C1 (en) * 2015-08-03 2016-10-10 Федеральное государственное казенное военное образовательное учреждение высшего профессионального образования "Военный учебно-научный центр Военно-воздушных сил "Военно-воздушная академия имени профессора Н.Е. Жуковского и Ю.А. Гагарина" (г. Воронеж) Министерства обороны Российской Федерации Apparatus for evaluating efficiency of data exchange of communication system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2599532C1 (en) * 2015-08-03 2016-10-10 Федеральное государственное казенное военное образовательное учреждение высшего профессионального образования "Военный учебно-научный центр Военно-воздушных сил "Военно-воздушная академия имени профессора Н.Е. Жуковского и Ю.А. Гагарина" (г. Воронеж) Министерства обороны Российской Федерации Apparatus for evaluating efficiency of data exchange of communication system

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