JPS57141128A - Complementary mos logical circuit - Google Patents

Complementary mos logical circuit

Info

Publication number
JPS57141128A
JPS57141128A JP56026376A JP2637681A JPS57141128A JP S57141128 A JPS57141128 A JP S57141128A JP 56026376 A JP56026376 A JP 56026376A JP 2637681 A JP2637681 A JP 2637681A JP S57141128 A JPS57141128 A JP S57141128A
Authority
JP
Japan
Prior art keywords
mos41
supplied
base
buffer circuit
logical circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56026376A
Other languages
Japanese (ja)
Inventor
Yasoji Suzuki
Kenji Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56026376A priority Critical patent/JPS57141128A/en
Priority to DE8282101282T priority patent/DE3274039D1/en
Priority to EP82101282A priority patent/EP0058958B1/en
Priority to CA000396984A priority patent/CA1188755A/en
Publication of JPS57141128A publication Critical patent/JPS57141128A/en
Priority to US06/652,429 priority patent/US4558234A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To hold high-speed operation by lowering the threshold voltage of a C- MOS curcuit and by generating its output signal through a buffer circuit. CONSTITUTION:A CMOS circuit 42 constituted by connecting a P-MOS41 and an N-MOS42 in series is provided between power sources VDD and VSS. An input signal IN is supplied to the gates of the P-MOS41 and N-MOS42. A signal phi1 appearing at the source of the P-MOS41 is supplied to the base of the transistor (TR)45 of a buffer circuit 44. The input signal IN is also supplied to the base of an N-MOS46 grounding the base of the TR45. Thus, the TR45 having a large factor of amplification and the N-MOS46 having a large coefficient of a source- drain current constitute the buffer circuit, so a logical circuit having a high operation speed is constituted.
JP56026376A 1981-02-25 1981-02-25 Complementary mos logical circuit Pending JPS57141128A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP56026376A JPS57141128A (en) 1981-02-25 1981-02-25 Complementary mos logical circuit
DE8282101282T DE3274039D1 (en) 1981-02-25 1982-02-19 Complementary mosfet logic circuit
EP82101282A EP0058958B1 (en) 1981-02-25 1982-02-19 Complementary mosfet logic circuit
CA000396984A CA1188755A (en) 1981-02-25 1982-02-24 Complementary mosfet logic circuit
US06/652,429 US4558234A (en) 1981-02-25 1984-09-20 Complementary MOSFET logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56026376A JPS57141128A (en) 1981-02-25 1981-02-25 Complementary mos logical circuit

Publications (1)

Publication Number Publication Date
JPS57141128A true JPS57141128A (en) 1982-09-01

Family

ID=12191791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56026376A Pending JPS57141128A (en) 1981-02-25 1981-02-25 Complementary mos logical circuit

Country Status (1)

Country Link
JP (1) JPS57141128A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63240126A (en) * 1987-03-27 1988-10-05 Toshiba Corp Bimos logic circuit
JPS6481414A (en) * 1987-09-24 1989-03-27 Hitachi Ltd Semiconductor logic circuit
JPH02143711A (en) * 1988-11-25 1990-06-01 Nec Corp Transistor circuit
JPH057138A (en) * 1991-06-27 1993-01-14 Nec Corp Semiconductor integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5387187A (en) * 1977-01-12 1978-08-01 Hitachi Ltd Semiconductor driving circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5387187A (en) * 1977-01-12 1978-08-01 Hitachi Ltd Semiconductor driving circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63240126A (en) * 1987-03-27 1988-10-05 Toshiba Corp Bimos logic circuit
JPS6481414A (en) * 1987-09-24 1989-03-27 Hitachi Ltd Semiconductor logic circuit
JPH02143711A (en) * 1988-11-25 1990-06-01 Nec Corp Transistor circuit
JPH057138A (en) * 1991-06-27 1993-01-14 Nec Corp Semiconductor integrated circuit

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