JPS57154612A - Digital modulating and demodulating system - Google Patents
Digital modulating and demodulating systemInfo
- Publication number
- JPS57154612A JPS57154612A JP4068881A JP4068881A JPS57154612A JP S57154612 A JPS57154612 A JP S57154612A JP 4068881 A JP4068881 A JP 4068881A JP 4068881 A JP4068881 A JP 4068881A JP S57154612 A JPS57154612 A JP S57154612A
- Authority
- JP
- Japan
- Prior art keywords
- code word
- bits
- bit
- code
- converted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To improve a high density recording, by reducing a maximum interval of magnetization inversion to facilitate clock regeneration by converting specific code word and code sequence in accordance with values of prescribed bits of three code words based on the 3PM system. CONSTITUTION:In the modulation based on the 3PM system, when the second- the sixth bits of a code word M are all 0 and the first and the second bits of a next code word N are 0, the sixth bit of a code word L preceding the code word M is set to 1 and the code word M is converted to 001001 if the second- the fifth bits of the code word L are all 0. If the second - the fifth bits of the code word L are not all 0, the code word M is converted to 001001; and when the second bit and the fifth bit of the code word M are 1 and 0 respectively and the first - the fourth bits of the code word N are all 0, the sixth bit of the code word M is set to 1 and pattern 001000 is used instead of the code word N. Further, the code word M after conversion is subjected to a prescribed conversion in accordance with values of the code word N and a next code word 0.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4068881A JPS57154612A (en) | 1981-03-20 | 1981-03-20 | Digital modulating and demodulating system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4068881A JPS57154612A (en) | 1981-03-20 | 1981-03-20 | Digital modulating and demodulating system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57154612A true JPS57154612A (en) | 1982-09-24 |
Family
ID=12587484
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4068881A Pending JPS57154612A (en) | 1981-03-20 | 1981-03-20 | Digital modulating and demodulating system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57154612A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59214358A (en) * | 1983-02-15 | 1984-12-04 | ヒュンダイ、エレクトロニクス、インダストリーズ、カムパニー、リミテッド | Group coding system for transmitting serial data |
-
1981
- 1981-03-20 JP JP4068881A patent/JPS57154612A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59214358A (en) * | 1983-02-15 | 1984-12-04 | ヒュンダイ、エレクトロニクス、インダストリーズ、カムパニー、リミテッド | Group coding system for transmitting serial data |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
NZ210858A (en) | Digital information transmission with code conversion to limit disparity | |
US3422425A (en) | Conversion from nrz code to selfclocking code | |
ES8607648A1 (en) | Digital data converting methods and apparatus. | |
GB1483810A (en) | Circuit for automatically correcting the timing of clock pulses in self-clocked pulse/signal decoders | |
JPS57154612A (en) | Digital modulating and demodulating system | |
DE3062710D1 (en) | Method and device for transmitting a binary sequence | |
JPS6457825A (en) | 4/5 code conversion system | |
JPS5750309A (en) | Encoding and decoding system for binary data | |
JPS57154611A (en) | Digital modulating and demodulating system | |
JPS5483411A (en) | Binary data coding system | |
JPS5666947A (en) | Data transmission method | |
FR2410921A1 (en) | Binary data coding and decoding system - uses transforming circuit reducing distortions due to successive regenerations of digital transmission | |
JPS57147108A (en) | Digital signal modulation and demodulation system | |
JPS54130111A (en) | Coding system | |
JPS52103902A (en) | Code error correcting method | |
JPS5473014A (en) | High density digital magnetic recording system | |
JPS5619507A (en) | Coding system | |
JPS57147116A (en) | Binary information modulating system | |
JPS5369017A (en) | Binary data coding system | |
JPS6457827A (en) | 4/5 nrzi code conversion system | |
JPS57176519A (en) | Digital modulation and demodulation system | |
JPS57154610A (en) | Digital modulating and demodulating system | |
JPS57130214A (en) | Digital modulation and demodulation system | |
JPS57207457A (en) | Sc bit superimposing system | |
JPS556961A (en) | Error control system |