JPS57154611A - Digital modulating and demodulating system - Google Patents
Digital modulating and demodulating systemInfo
- Publication number
- JPS57154611A JPS57154611A JP4068781A JP4068781A JPS57154611A JP S57154611 A JPS57154611 A JP S57154611A JP 4068781 A JP4068781 A JP 4068781A JP 4068781 A JP4068781 A JP 4068781A JP S57154611 A JPS57154611 A JP S57154611A
- Authority
- JP
- Japan
- Prior art keywords
- bit
- code word
- pattern
- code
- bits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
PURPOSE:To record data with a high density, by reducing a maximum interval of magnetization inversion to facilitate clock regeneration, by converting specific code word and code sequence when prescribed bits of two code words based on the 3PM system are 0. CONSTITUTION:In the modulation of data signals based on the 3PM system, when all bits from the second bit to the sixth bit of a code word A are 0 and the first bit and the second bit of a next code word B are 0, pattern 001001 is used as the code word instead of the code word A. When the second bit and the fifth bit of the code word A are 1 and 0 respectively and all bits from the first bit to the fourth bit of the code word B are 0, the sixth bit of the code word A is set to 1, and pattern 001000 is used as the code word instead of the code word B. Further, pattern 101 in a code sequence obtained by conversion is converted to pattern 010. For example, a modulating circuit (a) and a demodulating circuit (b) shown in figures are used to perform magnetic recording and reproducing in this manner.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4068781A JPS57154611A (en) | 1981-03-20 | 1981-03-20 | Digital modulating and demodulating system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4068781A JPS57154611A (en) | 1981-03-20 | 1981-03-20 | Digital modulating and demodulating system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57154611A true JPS57154611A (en) | 1982-09-24 |
Family
ID=12587454
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4068781A Pending JPS57154611A (en) | 1981-03-20 | 1981-03-20 | Digital modulating and demodulating system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57154611A (en) |
-
1981
- 1981-03-20 JP JP4068781A patent/JPS57154611A/en active Pending
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