JPS57153448A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS57153448A
JPS57153448A JP3848381A JP3848381A JPS57153448A JP S57153448 A JPS57153448 A JP S57153448A JP 3848381 A JP3848381 A JP 3848381A JP 3848381 A JP3848381 A JP 3848381A JP S57153448 A JPS57153448 A JP S57153448A
Authority
JP
Japan
Prior art keywords
wiring
windows
alloy
poly
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3848381A
Other languages
Japanese (ja)
Inventor
Hideo Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3848381A priority Critical patent/JPS57153448A/en
Publication of JPS57153448A publication Critical patent/JPS57153448A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the reliability and yield of a device by forming a Si film under Al wiring or connecting one part of the wiring of a Si-Al alloy to an element and shaping a window to an insulating film at the outside of the wiring on the surface of a Si substrate when the substrate to which the element is formed is coated, the window is shaped to the insulating film and Al is wired. CONSTITUTION:A P base and an N omitter are formed to a region 4 obtained by isolating an N epitaxial layer on the P type Si substrate by a P layer 3, the surface is coated with the insulating film 7 and the windows are molded. When poly Si and Al are laminated and the electrode wiring 9B, 9E, 9C are manufactured, projections are formed onto the wiring even when using the Al-Si alloy, and disconnection and wiring width are reduced. On the other hand, a projection is not formed when the wiring only of Al and in the exposed section of single crystal Si. The windows 11 are shaped at the outside of an element forming region along both sides of the wiring 9E by utilizing the phenomenon, and the windows are covered with poly Si and Al. When such structure, the projection is not molded to Al for wiring, and the yield and reliability of the IC are improved. Even when the windows 11 are exposed, effect is not affected. Even when the Si-Al alloy is used in place of the poly Si in order to prevent the spike of the alloy, the structure is effective.
JP3848381A 1981-03-17 1981-03-17 Semiconductor integrated circuit Pending JPS57153448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3848381A JPS57153448A (en) 1981-03-17 1981-03-17 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3848381A JPS57153448A (en) 1981-03-17 1981-03-17 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS57153448A true JPS57153448A (en) 1982-09-22

Family

ID=12526498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3848381A Pending JPS57153448A (en) 1981-03-17 1981-03-17 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS57153448A (en)

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