JPS57145361A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS57145361A JPS57145361A JP56030310A JP3031081A JPS57145361A JP S57145361 A JPS57145361 A JP S57145361A JP 56030310 A JP56030310 A JP 56030310A JP 3031081 A JP3031081 A JP 3031081A JP S57145361 A JPS57145361 A JP S57145361A
- Authority
- JP
- Japan
- Prior art keywords
- film
- type
- layer
- region
- type region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 239000010410 layer Substances 0.000 abstract 4
- 239000012535 impurity Substances 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 239000013078 crystal Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 abstract 1
- 239000012212 insulator Substances 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 abstract 1
- 238000005224 laser annealing Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To obtain C-MOSIC having high integration and no bi-polar effect by preparing N-channel and P-channel transistors in such a manner that they are overlaped each other vertically. CONSTITUTION:A thick field oxide film 102 is formed at the peripheral part of an N type Si substrate 101, a thin gate oxide film 103 is connected to an active region surrounded by the film 102, and a gate electrode 104 of polycrystalline Si containing N type impurities is provided in the central part of the film 103 so as to surround an oxide film 105. Next, by using this film as a mask, a P type region 106 is formed diffusely in active regions on both sides of the film 105, a polycrystalline Si layer containing P type impurities is grown on the whole surface and subjected to laser annealing and thereby a P type single crystal layer 107 is formed. Afterward, an N type region 108 is formed diffusely in the layer 107 located on both sides of the gate electrode 104, the layer 107 in an inactive region which is an unnecessary part is removed by the photoetching method, an inter-layer insulator film 109 is grown on the whole surface by the CVD method, an opening 110 is provided, Al wiring electrodes 111 are connected to the P type region 106 and N type region 108 respectively, and thus a device having a three- dimensional structure is prepared.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56030310A JPS57145361A (en) | 1981-03-03 | 1981-03-03 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56030310A JPS57145361A (en) | 1981-03-03 | 1981-03-03 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57145361A true JPS57145361A (en) | 1982-09-08 |
Family
ID=12300199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56030310A Pending JPS57145361A (en) | 1981-03-03 | 1981-03-03 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57145361A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57192081A (en) * | 1981-05-19 | 1982-11-26 | Ibm | Field effect transistor unit |
| JPS59103380A (en) * | 1982-11-09 | 1984-06-14 | ノーザン・テレコム・リミテッド | Laminated mos transistor |
-
1981
- 1981-03-03 JP JP56030310A patent/JPS57145361A/en active Pending
Non-Patent Citations (2)
| Title |
|---|
| IBM TECHNICAL DISCLOSURE BULLETIN=1973US * |
| IEEE ELECTRON DEVICE LETTERS=1980 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57192081A (en) * | 1981-05-19 | 1982-11-26 | Ibm | Field effect transistor unit |
| JPH0325949B2 (en) * | 1981-05-19 | 1991-04-09 | Intaanashonaru Bijinesu Mashiinzu Corp | |
| JPS59103380A (en) * | 1982-11-09 | 1984-06-14 | ノーザン・テレコム・リミテッド | Laminated mos transistor |
| JPH0530075B2 (en) * | 1982-11-09 | 1993-05-07 | Northern Telecom Ltd |
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