JPS57127994A - Storage device - Google Patents
Storage deviceInfo
- Publication number
- JPS57127994A JPS57127994A JP1121781A JP1121781A JPS57127994A JP S57127994 A JPS57127994 A JP S57127994A JP 1121781 A JP1121781 A JP 1121781A JP 1121781 A JP1121781 A JP 1121781A JP S57127994 A JPS57127994 A JP S57127994A
- Authority
- JP
- Japan
- Prior art keywords
- write
- ram
- rom
- memory address
- capacity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
Abstract
PURPOSE:To enable to give the function the same as a page capacity of an RAM to an ROM in combination with a small capacity of RAM, by providing a write-in display bit to a write-in RAM page storage memory, corresponding to each block of a large capacity of ROM. CONSTITUTION:Corresponding to blocks split into a plurality of a large capacity ROM 1, a write-in display bit field 31 is provided at a write-in RAM page storage memory 3, and when a new rewrite request to the ROM 1 is caused, the write-in display bit corresponding to the block including the memeory address in response to the write-in information is set to write-in display state, and the write-in information is written in the memory address of a RAM 2 with comparatively small capacity corresponded with a predetermined rule to this memory address. When the readout request to the memory address included in the block set already to the write-in display state for the display bit is present, the content corresponding to the memory address is read out from the RAM 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1121781A JPS57127994A (en) | 1981-01-28 | 1981-01-28 | Storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1121781A JPS57127994A (en) | 1981-01-28 | 1981-01-28 | Storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57127994A true JPS57127994A (en) | 1982-08-09 |
Family
ID=11771795
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1121781A Pending JPS57127994A (en) | 1981-01-28 | 1981-01-28 | Storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57127994A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10187529A (en) * | 1996-10-31 | 1998-07-21 | Internatl Business Mach Corp <Ibm> | System and method for enabling load at write time of dynamic rom data |
-
1981
- 1981-01-28 JP JP1121781A patent/JPS57127994A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10187529A (en) * | 1996-10-31 | 1998-07-21 | Internatl Business Mach Corp <Ibm> | System and method for enabling load at write time of dynamic rom data |
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