JPS5640347A - Data transmission system - Google Patents

Data transmission system

Info

Publication number
JPS5640347A
JPS5640347A JP11659079A JP11659079A JPS5640347A JP S5640347 A JPS5640347 A JP S5640347A JP 11659079 A JP11659079 A JP 11659079A JP 11659079 A JP11659079 A JP 11659079A JP S5640347 A JPS5640347 A JP S5640347A
Authority
JP
Japan
Prior art keywords
transmitted
data
frame data
processing means
operation processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11659079A
Other languages
Japanese (ja)
Inventor
Shigeo Shin
Akira Matsuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP11659079A priority Critical patent/JPS5640347A/en
Publication of JPS5640347A publication Critical patent/JPS5640347A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To shorten the transmission time, by adding a separator code between respective commands to set plural commands to one-frame data in case that plural kinds of command to be transmitted as data exist. CONSTITUTION:The number of characters to be transmitted in one frame is arranged in the first character of one-frame data to be transmitted from central processing unit 1 to terminal unit 10A, and a separator code to distinguish the next command is arranged following data characters, and a check code is added to the last character. When one-frame data including plural commands is transmitted from central processing unit 1, direct memory access control circuit 15 receives it and gives the HOLD signal to operation processing means 13. Then, the word length of one-frame data is written in memory 16, and the operation processing means is interrupted. The operation processing means skips the above-mentioned separator code and transfers command data to the storage area successively.
JP11659079A 1979-09-10 1979-09-10 Data transmission system Pending JPS5640347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11659079A JPS5640347A (en) 1979-09-10 1979-09-10 Data transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11659079A JPS5640347A (en) 1979-09-10 1979-09-10 Data transmission system

Publications (1)

Publication Number Publication Date
JPS5640347A true JPS5640347A (en) 1981-04-16

Family

ID=14690896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11659079A Pending JPS5640347A (en) 1979-09-10 1979-09-10 Data transmission system

Country Status (1)

Country Link
JP (1) JPS5640347A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6019341A (en) * 1983-07-13 1985-01-31 Usac Electronics Ind Co Ltd Line control system
JPH06290117A (en) * 1993-04-05 1994-10-18 Nec Corp Network system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6019341A (en) * 1983-07-13 1985-01-31 Usac Electronics Ind Co Ltd Line control system
JPH06290117A (en) * 1993-04-05 1994-10-18 Nec Corp Network system

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