JPS57121231A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS57121231A JPS57121231A JP637181A JP637181A JPS57121231A JP S57121231 A JPS57121231 A JP S57121231A JP 637181 A JP637181 A JP 637181A JP 637181 A JP637181 A JP 637181A JP S57121231 A JPS57121231 A JP S57121231A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- shape groove
- mask
- polycrystalline
- making
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 4
- 238000004519 manufacturing process Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
PURPOSE:To facilitate formation of a minute U shape groove in a semiconductor device by a method wherein polycrystalline semiconductor layer provided on a semiconductor substrate interposing an insulating film between them is patternized, and the substrate is etched making the polycrystalline layer and the insulating film thereof as the mask. CONSTITUTION:The polycrystalline Si layer 3 is provided on the Si substrate 1 interposing the SiO2 film 2 between them, an N<+> layer is formed by diffusion making an Si3N4 film formed along the necessitated U shape groove as the mask, and after the surface thereof is oxidized thermally, the Si3N4 film is removed, minute breath of the exposed N<+> region only is etched to be removed by selective etching according to difference of concentration of impurities, the insulating film 2 is patternized making the polycrystalline Si layer thereof as the mask, the U shape groove is formed in the substrate 1 making the insulating film thereof as the mask, and the U shape groove is buried up with an SiO2 layer by thermall oxidation. Accordingly the minute U shape groove can be formed extremely precisely without according to the photoetching treatment technique.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP637181A JPS57121231A (en) | 1981-01-21 | 1981-01-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP637181A JPS57121231A (en) | 1981-01-21 | 1981-01-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57121231A true JPS57121231A (en) | 1982-07-28 |
Family
ID=11636503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP637181A Pending JPS57121231A (en) | 1981-01-21 | 1981-01-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57121231A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5976445A (en) * | 1982-10-26 | 1984-05-01 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1981
- 1981-01-21 JP JP637181A patent/JPS57121231A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5976445A (en) * | 1982-10-26 | 1984-05-01 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
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