JPS57120294A - Memory control circuit - Google Patents
Memory control circuitInfo
- Publication number
- JPS57120294A JPS57120294A JP56006870A JP687081A JPS57120294A JP S57120294 A JPS57120294 A JP S57120294A JP 56006870 A JP56006870 A JP 56006870A JP 687081 A JP687081 A JP 687081A JP S57120294 A JPS57120294 A JP S57120294A
- Authority
- JP
- Japan
- Prior art keywords
- current
- control signal
- trs
- depletion type
- writing operation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
Abstract
PURPOSE:To reduce current consumption for writing operation, by applying a signal, which has different voltage levels for reading operation and writing operation, in series to load transistors (TR) of transistor logical gates constituting the decoder of a memory control circuit. CONSTITUTION:Between a power source Vcc and the drain of the load TR1 of a decoder circuit composed of E/D type MOSTRs, a depletion type field effect TR5 is connected in series. The gate of the TR5 is connected to a control signal S. The control signal S has logic ''1'' during the reading operation of the decoder circuit and logic ''0'' during the writing operation. The depletion type TRs are normally turned on and the current of each TR varies with its gate voltage. Mutual conductance gm is 2k(VGS-VT), where (k) is a proportional constant determined by the structure of the TRs, and a current IDS flowing through the depletion type TRs is gm<2>/4k. For this purpose, when the control signal S has the ''1'', the current is flowed more and when the ''0'', the current is reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56006870A JPS57120294A (en) | 1981-01-19 | 1981-01-19 | Memory control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56006870A JPS57120294A (en) | 1981-01-19 | 1981-01-19 | Memory control circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57120294A true JPS57120294A (en) | 1982-07-27 |
JPS6216471B2 JPS6216471B2 (en) | 1987-04-13 |
Family
ID=11650261
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56006870A Granted JPS57120294A (en) | 1981-01-19 | 1981-01-19 | Memory control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57120294A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6196588A (en) * | 1984-10-16 | 1986-05-15 | Mitsubishi Electric Corp | Semiconductor memory device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02113163U (en) * | 1988-06-30 | 1990-09-11 |
-
1981
- 1981-01-19 JP JP56006870A patent/JPS57120294A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6196588A (en) * | 1984-10-16 | 1986-05-15 | Mitsubishi Electric Corp | Semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
JPS6216471B2 (en) | 1987-04-13 |
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