JPS57117035A - Data transfer device of asynchronous device - Google Patents
Data transfer device of asynchronous deviceInfo
- Publication number
- JPS57117035A JPS57117035A JP443581A JP443581A JPS57117035A JP S57117035 A JPS57117035 A JP S57117035A JP 443581 A JP443581 A JP 443581A JP 443581 A JP443581 A JP 443581A JP S57117035 A JPS57117035 A JP S57117035A
- Authority
- JP
- Japan
- Prior art keywords
- buffer
- data
- outputted
- dma
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Information Transfer Systems (AREA)
Abstract
PURPOSE:To eliminate a loss of a data, by providing a buffer even if a device for which other DMA control is required is connected to the same computer, when executing the DMA of plural words. CONSTITUTION:In case when a data is transferred to a main storage device 2 from an external device 9, a signal from a synchronizing circuit 6 and each data having a frame number, from a gate circuit 8 are outputted to a buffer 11 and a buffer 4. A controlling circuit 7 outputs a signal to a gate circuit 13 so that the frame number is outputted to an address generating circuit 3 of the main storage device from the buffer 11, the first DMA signal is outputted to the buffers 11, 4, respectively, a data of the buffer 11 is written in the main storage device 2, and a data of the buffer 4 is shifted to the buffer 11. When the second DMA request signal is outputted in time T2 after the first output, a data in the buffer 11 is written in the next address of the device 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP443581A JPS57117035A (en) | 1981-01-14 | 1981-01-14 | Data transfer device of asynchronous device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP443581A JPS57117035A (en) | 1981-01-14 | 1981-01-14 | Data transfer device of asynchronous device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57117035A true JPS57117035A (en) | 1982-07-21 |
JPS619656B2 JPS619656B2 (en) | 1986-03-25 |
Family
ID=11584152
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP443581A Granted JPS57117035A (en) | 1981-01-14 | 1981-01-14 | Data transfer device of asynchronous device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57117035A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6118060A (en) * | 1984-07-04 | 1986-01-25 | Nec Corp | Data processing system |
-
1981
- 1981-01-14 JP JP443581A patent/JPS57117035A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6118060A (en) * | 1984-07-04 | 1986-01-25 | Nec Corp | Data processing system |
Also Published As
Publication number | Publication date |
---|---|
JPS619656B2 (en) | 1986-03-25 |
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