JPS57114923A - Peripheral device controller in data processing system - Google Patents

Peripheral device controller in data processing system

Info

Publication number
JPS57114923A
JPS57114923A JP56001165A JP116581A JPS57114923A JP S57114923 A JPS57114923 A JP S57114923A JP 56001165 A JP56001165 A JP 56001165A JP 116581 A JP116581 A JP 116581A JP S57114923 A JPS57114923 A JP S57114923A
Authority
JP
Japan
Prior art keywords
bus
parity
data
outputted
adaptor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56001165A
Other languages
English (en)
Other versions
JPS6119051B2 (ja
Inventor
Ichirou Shirosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56001165A priority Critical patent/JPS57114923A/ja
Publication of JPS57114923A publication Critical patent/JPS57114923A/ja
Publication of JPS6119051B2 publication Critical patent/JPS6119051B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
JP56001165A 1981-01-09 1981-01-09 Peripheral device controller in data processing system Granted JPS57114923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56001165A JPS57114923A (en) 1981-01-09 1981-01-09 Peripheral device controller in data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56001165A JPS57114923A (en) 1981-01-09 1981-01-09 Peripheral device controller in data processing system

Publications (2)

Publication Number Publication Date
JPS57114923A true JPS57114923A (en) 1982-07-17
JPS6119051B2 JPS6119051B2 (ja) 1986-05-15

Family

ID=11493820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56001165A Granted JPS57114923A (en) 1981-01-09 1981-01-09 Peripheral device controller in data processing system

Country Status (1)

Country Link
JP (1) JPS57114923A (ja)

Also Published As

Publication number Publication date
JPS6119051B2 (ja) 1986-05-15

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