JPS57107642A - Counter reset system - Google Patents
Counter reset systemInfo
- Publication number
- JPS57107642A JPS57107642A JP18492780A JP18492780A JPS57107642A JP S57107642 A JPS57107642 A JP S57107642A JP 18492780 A JP18492780 A JP 18492780A JP 18492780 A JP18492780 A JP 18492780A JP S57107642 A JPS57107642 A JP S57107642A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- reset pulse
- timing
- address
- sampling clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/38—Starting, stopping or resetting the counter
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To prevent malfunction accompanied with jitter of a reset pulse, by providing a reset pulse insertion address to a data channel address which is generated, in a timing generating circuit provided with a counter. CONSTITUTION:A timing generating circuit 1 consists of a counter CTR, it is driven with a reference clock, and supplies a timing signal to a data processing circuit. A reset pulse generating circuit 2 consists of flip-flops FF1, FF2 and a NAND circuit ND, and to the circuit 2, a sampling clock (2) and a reset timing pulse (3) from a frequency division circuit 3 are supplied. When a data channel address of a timing signal (1) is at a maximum frequency, the sampling clock is selected to the double frequency, and even if the phase of the sampling clock is changed, a reset pulse (6) is always generated in a dummy address.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18492780A JPS57107642A (en) | 1980-12-25 | 1980-12-25 | Counter reset system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18492780A JPS57107642A (en) | 1980-12-25 | 1980-12-25 | Counter reset system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57107642A true JPS57107642A (en) | 1982-07-05 |
Family
ID=16161767
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18492780A Pending JPS57107642A (en) | 1980-12-25 | 1980-12-25 | Counter reset system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57107642A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100612265B1 (en) | 2004-09-07 | 2006-08-14 | 삼성전자주식회사 | Apparatus for reset stablization and method for generating reset signal thereof |
-
1980
- 1980-12-25 JP JP18492780A patent/JPS57107642A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100612265B1 (en) | 2004-09-07 | 2006-08-14 | 삼성전자주식회사 | Apparatus for reset stablization and method for generating reset signal thereof |
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