JPS57105895A - Error detection and correction device - Google Patents

Error detection and correction device

Info

Publication number
JPS57105895A
JPS57105895A JP55182200A JP18220080A JPS57105895A JP S57105895 A JPS57105895 A JP S57105895A JP 55182200 A JP55182200 A JP 55182200A JP 18220080 A JP18220080 A JP 18220080A JP S57105895 A JPS57105895 A JP S57105895A
Authority
JP
Japan
Prior art keywords
circuit
data
error
rewrite
readout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55182200A
Other languages
Japanese (ja)
Inventor
Hiroshi Goto
Katsuichi Tomita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55182200A priority Critical patent/JPS57105895A/en
Publication of JPS57105895A publication Critical patent/JPS57105895A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To avoid useless error logging, by providing a rewrite-in circuit rewriting a corrected data to a storage device when a correctable error is detected and a control circuit performing control based on the result discriminated by rewrite-in. CONSTITUTION:Data read out at a readout circuit 20 from a storage device 10 is checked for the presence of error at an error detection and correction circuit 30, and the output data is transmitted to a control circuit 50. If the address storing the data is not recorded in the circuit 50, the circuit 50 instructs rewrite- in to the storage device 10, the data is transferred from the circuit 60 to a line 112 to make rewrite-in to the storage device 10. After rewrite-in, when a re- readout instruction signal is started via a signal line 109, the re-readout of this data is made at the readout circuit 20. After the re-readout of the data, if the error correction is informed to the circuit 50 for the data at the circuit 30, an error report instruction signal is transmitted to an error report circuit 40 and the error information is transmitted via a signal line 107.
JP55182200A 1980-12-22 1980-12-22 Error detection and correction device Pending JPS57105895A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55182200A JPS57105895A (en) 1980-12-22 1980-12-22 Error detection and correction device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55182200A JPS57105895A (en) 1980-12-22 1980-12-22 Error detection and correction device

Publications (1)

Publication Number Publication Date
JPS57105895A true JPS57105895A (en) 1982-07-01

Family

ID=16114096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55182200A Pending JPS57105895A (en) 1980-12-22 1980-12-22 Error detection and correction device

Country Status (1)

Country Link
JP (1) JPS57105895A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60189555A (en) * 1984-03-09 1985-09-27 Daikin Ind Ltd Memory device
JPS6339061A (en) * 1986-08-04 1988-02-19 Fujitsu Ltd Processing system for memory error

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60189555A (en) * 1984-03-09 1985-09-27 Daikin Ind Ltd Memory device
JPS6339061A (en) * 1986-08-04 1988-02-19 Fujitsu Ltd Processing system for memory error

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