JPS57105070A - Control system of register interference - Google Patents

Control system of register interference

Info

Publication number
JPS57105070A
JPS57105070A JP18225280A JP18225280A JPS57105070A JP S57105070 A JPS57105070 A JP S57105070A JP 18225280 A JP18225280 A JP 18225280A JP 18225280 A JP18225280 A JP 18225280A JP S57105070 A JPS57105070 A JP S57105070A
Authority
JP
Japan
Prior art keywords
instruction
processor
register
flag
decoded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18225280A
Other languages
Japanese (ja)
Other versions
JPS5829549B2 (en
Inventor
Kiyosumi Sato
Yoshihiro Mizushima
Keiichiro Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18225280A priority Critical patent/JPS5829549B2/en
Publication of JPS57105070A publication Critical patent/JPS57105070A/en
Publication of JPS5829549B2 publication Critical patent/JPS5829549B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To perform the interlock control, by giving a flag in case the writing of a register is carried out to an instruction exclusive for a slave processor and accordingly deciding whether a general-purpose register is used or not. CONSTITUTION:The instruction given from a main processor 1 is decoded and executed by a slave processor 2, and the result of the decoding and execution is stored in a main storage device 3, the own arithmetic register, a general- purpose register 4 in the processor 1, etc. according to respective instructions. On the other hand, the instruction read out of the device 3 is decoded at the processor through an instruction decoder circuit 5. In case the instruction is used exclusively for the processor 2, a start signal showing the start of execution of the instruction is sent to the processor 2. When the processor 1 decodes the instruction exclusively used for the processor 2, a flag 6 is given for the use of the specific register 4. With the setting of the flag 6, the process is discontinued for an ordinary instruction using the register 4 until an instruction end signal is received from the processor 2. Then the flag 6 is reset by the end signal to restart the pocess of the ordinary instruction.
JP18225280A 1980-12-23 1980-12-23 Register interference control method Expired JPS5829549B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18225280A JPS5829549B2 (en) 1980-12-23 1980-12-23 Register interference control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18225280A JPS5829549B2 (en) 1980-12-23 1980-12-23 Register interference control method

Publications (2)

Publication Number Publication Date
JPS57105070A true JPS57105070A (en) 1982-06-30
JPS5829549B2 JPS5829549B2 (en) 1983-06-23

Family

ID=16115000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18225280A Expired JPS5829549B2 (en) 1980-12-23 1980-12-23 Register interference control method

Country Status (1)

Country Link
JP (1) JPS5829549B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59201154A (en) * 1983-04-18 1984-11-14 モトロ−ラ・インコ−ポレ−テツド Method and apparatus for adjusting execution of instruction by joint processor
JPS61170830A (en) * 1985-01-25 1986-08-01 Fujitsu Ltd Register reference control system
JPS61170829A (en) * 1985-01-25 1986-08-01 Fujitsu Ltd Writing control system of register
EP0231526A2 (en) * 1986-01-08 1987-08-12 Hitachi, Ltd. Multi-processor system
US6832117B1 (en) 1999-09-22 2004-12-14 Kabushiki Kaisha Toshiba Processor core for using external extended arithmetic unit efficiently and processor incorporating the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5885740A (en) * 1981-11-16 1983-05-23 Nissan Motor Co Ltd Fitting structure of bumper
JPS63108874U (en) * 1987-01-07 1988-07-13

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59201154A (en) * 1983-04-18 1984-11-14 モトロ−ラ・インコ−ポレ−テツド Method and apparatus for adjusting execution of instruction by joint processor
JPS61170830A (en) * 1985-01-25 1986-08-01 Fujitsu Ltd Register reference control system
JPS61170829A (en) * 1985-01-25 1986-08-01 Fujitsu Ltd Writing control system of register
JPH0419575B2 (en) * 1985-01-25 1992-03-30 Fujitsu Ltd
JPH0419574B2 (en) * 1985-01-25 1992-03-30 Fujitsu Ltd
EP0231526A2 (en) * 1986-01-08 1987-08-12 Hitachi, Ltd. Multi-processor system
US4803620A (en) * 1986-01-08 1989-02-07 Hitachi, Ltd. Multi-processor system responsive to pause and pause clearing instructions for instruction execution control
US6832117B1 (en) 1999-09-22 2004-12-14 Kabushiki Kaisha Toshiba Processor core for using external extended arithmetic unit efficiently and processor incorporating the same
US7308320B2 (en) 1999-09-22 2007-12-11 Kabushiki Kaisha Toshiba Processor core for using external extended arithmetic unit efficiently and processor incorporating the same

Also Published As

Publication number Publication date
JPS5829549B2 (en) 1983-06-23

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