JPS5699567A - Array processor - Google Patents

Array processor

Info

Publication number
JPS5699567A
JPS5699567A JP42480A JP42480A JPS5699567A JP S5699567 A JPS5699567 A JP S5699567A JP 42480 A JP42480 A JP 42480A JP 42480 A JP42480 A JP 42480A JP S5699567 A JPS5699567 A JP S5699567A
Authority
JP
Japan
Prior art keywords
data
memory
control data
control
controlling part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP42480A
Other languages
Japanese (ja)
Inventor
Tsutomu Tenma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP42480A priority Critical patent/JPS5699567A/en
Publication of JPS5699567A publication Critical patent/JPS5699567A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Abstract

PURPOSE:To store the operation processing result into a memory in a high speed, by adding a circuit, which controls the combination between held and operated data without storing the intermediate calculation result, between the memory and the operating part and by performing the operation processing of array data stored in the memory by starting from the exterior. CONSTITUTION:Address data and control data are generated by memory controlling part 11, and data corresponding to the address is applied from memory 10 to controlling part 11, and control data from memory 10 and controlling part 11 are supplied to binomial data searching part 12. Control data and the operation parameter corresponding to control data are output by this searching part, and further, two data are operated according to the operation parameter in pipeline operating part 13, and operation resultant data and control data are input to output control part 14. New control data is generated according to control data from operating part 13 by controlling part 14 and is applied to control part 11 together with operation resultant data, and array data of several processing results is stored in memory 10 by controlling part 11.
JP42480A 1980-01-07 1980-01-07 Array processor Pending JPS5699567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP42480A JPS5699567A (en) 1980-01-07 1980-01-07 Array processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP42480A JPS5699567A (en) 1980-01-07 1980-01-07 Array processor

Publications (1)

Publication Number Publication Date
JPS5699567A true JPS5699567A (en) 1981-08-10

Family

ID=11473417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP42480A Pending JPS5699567A (en) 1980-01-07 1980-01-07 Array processor

Country Status (1)

Country Link
JP (1) JPS5699567A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58103037A (en) * 1981-12-14 1983-06-18 Nec Corp Queue memory device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5491158A (en) * 1977-12-28 1979-07-19 Fujitsu Ltd Vector operation control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5491158A (en) * 1977-12-28 1979-07-19 Fujitsu Ltd Vector operation control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58103037A (en) * 1981-12-14 1983-06-18 Nec Corp Queue memory device
JPH044630B2 (en) * 1981-12-14 1992-01-28

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