JPS5693193A - Ic memory test device - Google Patents

Ic memory test device

Info

Publication number
JPS5693193A
JPS5693193A JP17003379A JP17003379A JPS5693193A JP S5693193 A JPS5693193 A JP S5693193A JP 17003379 A JP17003379 A JP 17003379A JP 17003379 A JP17003379 A JP 17003379A JP S5693193 A JPS5693193 A JP S5693193A
Authority
JP
Japan
Prior art keywords
memory
error
test
exerciser
address stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17003379A
Other languages
Japanese (ja)
Inventor
Takatoshi Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17003379A priority Critical patent/JPS5693193A/en
Publication of JPS5693193A publication Critical patent/JPS5693193A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To realize a test for an IC memory containing a faulty bit, by ignoring a reading result of the IC memory for an error address stored in a fail memory.
CONSTITUTION: Various types of test patterns are applied to the IC memory 2 successively by the exerciser 3. In this case, if an error is detected with the reading of the memory 2, the error address stored previously in the fail memory 5 is masked to be excluded from to be the subject for decision of quality. Then the noncoincidence signal l8 is generated from the comparator 4 and in the memory address where the logic 0 is read out to the output of the memory 5, the error signal ERR is transmitted, and the exerciser 3 discontinues the generation of the test pattern, then the error lamp is displayed to complete a function test.
COPYRIGHT: (C)1981,JPO&Japio
JP17003379A 1979-12-26 1979-12-26 Ic memory test device Pending JPS5693193A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17003379A JPS5693193A (en) 1979-12-26 1979-12-26 Ic memory test device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17003379A JPS5693193A (en) 1979-12-26 1979-12-26 Ic memory test device

Publications (1)

Publication Number Publication Date
JPS5693193A true JPS5693193A (en) 1981-07-28

Family

ID=15897355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17003379A Pending JPS5693193A (en) 1979-12-26 1979-12-26 Ic memory test device

Country Status (1)

Country Link
JP (1) JPS5693193A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58155599A (en) * 1982-03-10 1983-09-16 Hitachi Ltd Memory tester
JPS61210975A (en) * 1985-03-15 1986-09-19 Sony Tektronix Corp Electronic circuit testing method
JPH01187469A (en) * 1987-10-30 1989-07-26 Teledyne Inc Leakage current tester

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58155599A (en) * 1982-03-10 1983-09-16 Hitachi Ltd Memory tester
JPS61210975A (en) * 1985-03-15 1986-09-19 Sony Tektronix Corp Electronic circuit testing method
JPH01187469A (en) * 1987-10-30 1989-07-26 Teledyne Inc Leakage current tester

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