JPS5692621A - Input/output processor - Google Patents

Input/output processor

Info

Publication number
JPS5692621A
JPS5692621A JP16977679A JP16977679A JPS5692621A JP S5692621 A JPS5692621 A JP S5692621A JP 16977679 A JP16977679 A JP 16977679A JP 16977679 A JP16977679 A JP 16977679A JP S5692621 A JPS5692621 A JP S5692621A
Authority
JP
Japan
Prior art keywords
execution
rank
rank system
instruction
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16977679A
Other languages
Japanese (ja)
Inventor
Hiroto Katsumata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16977679A priority Critical patent/JPS5692621A/en
Publication of JPS5692621A publication Critical patent/JPS5692621A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable to correctly response to the upper-rank system, by providing FF storing the instruction from the upper-rank system, inhibiting the function to the upper-rank system while the execution of initialized program and observing FF after the end of initialization.
CONSTITUTION: When the system power is on, the initialized program in a memory 2 is executed under the control of a processor 1. During the execution of program, when the instruction such as load is made via a bus 4 from the upper-rank system, it is stored in FF6. When the execution of initialization is finished and the initial set as the local system is finished, the operation based on the status stored in FF6 is made, the state of success and failure is added, and the result is answered to the upper-rank system via a system inteface unit 3 and upper-rank system bus 4. During the execution of initialized program, the instruction via the upper-rank system bus only can be received.
COPYRIGHT: (C)1981,JPO&Japio
JP16977679A 1979-12-26 1979-12-26 Input/output processor Pending JPS5692621A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16977679A JPS5692621A (en) 1979-12-26 1979-12-26 Input/output processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16977679A JPS5692621A (en) 1979-12-26 1979-12-26 Input/output processor

Publications (1)

Publication Number Publication Date
JPS5692621A true JPS5692621A (en) 1981-07-27

Family

ID=15892641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16977679A Pending JPS5692621A (en) 1979-12-26 1979-12-26 Input/output processor

Country Status (1)

Country Link
JP (1) JPS5692621A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58186828A (en) * 1982-04-26 1983-10-31 Oki Electric Ind Co Ltd Protecting circuit of peripheral equipment
JPS59220819A (en) * 1983-05-30 1984-12-12 Fujitsu Ltd Resetting circuit
JPS60134332A (en) * 1983-12-21 1985-07-17 Hitachi Ltd Magnetic disk control device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58186828A (en) * 1982-04-26 1983-10-31 Oki Electric Ind Co Ltd Protecting circuit of peripheral equipment
JPS59220819A (en) * 1983-05-30 1984-12-12 Fujitsu Ltd Resetting circuit
JPH037983B2 (en) * 1983-05-30 1991-02-04 Fujitsu Ltd
JPS60134332A (en) * 1983-12-21 1985-07-17 Hitachi Ltd Magnetic disk control device

Similar Documents

Publication Publication Date Title
JPS52122786A (en) Sequence controlling system
JPS57150019A (en) Control system of terminal device
JPS5692621A (en) Input/output processor
JPS5344134A (en) Microprogram control system
JPS54117640A (en) Memory address designation system
JPS5495133A (en) Input/output processing control system
JPS5532192A (en) Information processing device
JPS5647804A (en) Execution control device of sequential controller
JPS551676A (en) Memory protect system
JPS5437646A (en) Program loading system
JPS54154051A (en) Automatic load control system for marine generator
JPS51127637A (en) Information processing device under micro program control system
JPS57166605A (en) Sequence controller
JPS5453234A (en) Transmission fault processor controller
JPS5475961A (en) Microprogram address control system
JPS553043A (en) Microcomputer control circuit
JPS55159253A (en) Microprogram control unit
JPS54109340A (en) Remote loading controller
JPS55159257A (en) Debugging system
JPS54120547A (en) Microprogram memory controller
JPS55119729A (en) Data processor
JPS54134276A (en) Program timer
JPS5635207A (en) Automatic operation control device for power generation plant
JPS52101457A (en) Control circuit in control type power conversion circuit
JPS5588139A (en) Program write system