JPS5684096A - Digital exchange processing system - Google Patents
Digital exchange processing systemInfo
- Publication number
- JPS5684096A JPS5684096A JP16201579A JP16201579A JPS5684096A JP S5684096 A JPS5684096 A JP S5684096A JP 16201579 A JP16201579 A JP 16201579A JP 16201579 A JP16201579 A JP 16201579A JP S5684096 A JPS5684096 A JP S5684096A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- ch1in
- time
- address
- separating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
PURPOSE:To enable real-time exchange by providing a circuit with flexibility by providing a multiplexing circuit and separating circuit as a substitute for a memory device for connection address dial number storage and rearrangement. CONSTITUTION:Clock pulse CP (where N is the number of channels and fS is a communication speed) of frequency NXfS is supplied to 1/N counter 12 to generate timing pulses phi1-phiN and multiplexing circuit 11 sends encoded signal CD, inputted to respective channels CH1IN-CHNIN, to separating circuit 15 as a time-division multiplex signal. On the basis of a control indication signal, control circuit 13 informs separating circuit 15 of which address is assigned to which time slot. For example, address CHNOUT is assigned to time slot CH1IN and separating circuit 15 connects CH1IN to CHNOUT. Therefore this system does not take much time for exchange and provides the circuit with flexibility in comparison with the usual system that stores and makes rearrangement of connection address dial numbers by using a memory unit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16201579A JPS5684096A (en) | 1979-12-12 | 1979-12-12 | Digital exchange processing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16201579A JPS5684096A (en) | 1979-12-12 | 1979-12-12 | Digital exchange processing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5684096A true JPS5684096A (en) | 1981-07-09 |
Family
ID=15746421
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16201579A Pending JPS5684096A (en) | 1979-12-12 | 1979-12-12 | Digital exchange processing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5684096A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4516272A (en) * | 1982-02-15 | 1985-05-07 | Ricoh Company, Ltd. | Communication network |
-
1979
- 1979-12-12 JP JP16201579A patent/JPS5684096A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4516272A (en) * | 1982-02-15 | 1985-05-07 | Ricoh Company, Ltd. | Communication network |
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