JPS5679455A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5679455A JPS5679455A JP15707079A JP15707079A JPS5679455A JP S5679455 A JPS5679455 A JP S5679455A JP 15707079 A JP15707079 A JP 15707079A JP 15707079 A JP15707079 A JP 15707079A JP S5679455 A JPS5679455 A JP S5679455A
- Authority
- JP
- Japan
- Prior art keywords
- package
- capacitance
- pads
- electrode
- electrode layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To prevent the lowering of the integration degree by forming a capacitance between electrode layers inside and on the surface of a package so as to be connected to ICs incorporated. CONSTITUTION:An IC 11 is mounted in a recess 2 of a package 1 made of an alumina ceramic and connected to a diatouch 6, which is connected to an electrode layer 7 arranged in the package. Pads 10 on the top of IC are connected to a junction post 4 and one of the pads is connected to an electrode layer 7 with the same area arranged on the surface of the package 1 facing the electrode 7 to form a capacitance 9 between electrodes 7 and 8. This enables connection of a sufficient capacitance to a substrate or the like of a circuit without externally mounting additional capacitance.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15707079A JPS5679455A (en) | 1979-12-04 | 1979-12-04 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15707079A JPS5679455A (en) | 1979-12-04 | 1979-12-04 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5679455A true JPS5679455A (en) | 1981-06-30 |
Family
ID=15641567
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15707079A Pending JPS5679455A (en) | 1979-12-04 | 1979-12-04 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5679455A (en) |
-
1979
- 1979-12-04 JP JP15707079A patent/JPS5679455A/en active Pending
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