JPS5676551A - Transistor mount - Google Patents

Transistor mount

Info

Publication number
JPS5676551A
JPS5676551A JP15320279A JP15320279A JPS5676551A JP S5676551 A JPS5676551 A JP S5676551A JP 15320279 A JP15320279 A JP 15320279A JP 15320279 A JP15320279 A JP 15320279A JP S5676551 A JPS5676551 A JP S5676551A
Authority
JP
Japan
Prior art keywords
fet
manner
heat
insulating sheet
shielding case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15320279A
Other languages
Japanese (ja)
Other versions
JPS6033310B2 (en
Inventor
Shinichi Inoue
Toshio Chiaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15320279A priority Critical patent/JPS6033310B2/en
Publication of JPS5676551A publication Critical patent/JPS5676551A/en
Publication of JPS6033310B2 publication Critical patent/JPS6033310B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To insulating an FET in a DC manner and conduct the heat sink of the FET in an AC manner by interposing an insulating sheet between a metal for shielding and dissipating heat and a heat sink mounting plate and providing an electromagnetic absorber thereat. CONSTITUTION:A source-grounding type FET4 and both substrates 21, 26 are fixed on a heat conductive source mounting palte 31, which is fixed by screws 33, 34 insulated through a thin insulating sheet 32 from a shielding case 23. an electromagnetic wave absorbers 41, 42 are buried in a rectangular cross sectional groove at the bottom of the source mounting plate 31. Thus, the heat of the FET is dissipated through the thin insulating sheet 32 to the shielding case, is insulated in a DC manner and is ground to the shielding case in an AC manner. The feedback between the input and the output of the FET can be suppressed by absorbing the electromagnetic wave through a gap due to the absorber.
JP15320279A 1979-11-26 1979-11-26 transistor mount Expired JPS6033310B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15320279A JPS6033310B2 (en) 1979-11-26 1979-11-26 transistor mount

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15320279A JPS6033310B2 (en) 1979-11-26 1979-11-26 transistor mount

Publications (2)

Publication Number Publication Date
JPS5676551A true JPS5676551A (en) 1981-06-24
JPS6033310B2 JPS6033310B2 (en) 1985-08-02

Family

ID=15557266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15320279A Expired JPS6033310B2 (en) 1979-11-26 1979-11-26 transistor mount

Country Status (1)

Country Link
JP (1) JPS6033310B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583987B2 (en) * 1999-02-26 2003-06-24 Intel Corporation Electromagnetic interference and heatsinking

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583987B2 (en) * 1999-02-26 2003-06-24 Intel Corporation Electromagnetic interference and heatsinking

Also Published As

Publication number Publication date
JPS6033310B2 (en) 1985-08-02

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