JPS5673440A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5673440A
JPS5673440A JP15002879A JP15002879A JPS5673440A JP S5673440 A JPS5673440 A JP S5673440A JP 15002879 A JP15002879 A JP 15002879A JP 15002879 A JP15002879 A JP 15002879A JP S5673440 A JPS5673440 A JP S5673440A
Authority
JP
Japan
Prior art keywords
etching
film
sio2
mask
coated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15002879A
Other languages
Japanese (ja)
Inventor
Yukiya Takezaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15002879A priority Critical patent/JPS5673440A/en
Publication of JPS5673440A publication Critical patent/JPS5673440A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To obtain the smooth surface and to prevent the step disconnection on the coated film to be provided successively for the subject device by a method wherein a selective etching is performed on the eave of an SiO2 mask by changing the etching solution. CONSTITUTION:An etching is performed on the impurity-diffused layer 2 of an Si substrate 1 by a mixed solution of HF and HNO3 using an SiO2 mask and the protruding section of the mask 3' is formed. Then, when an etching is performed using a 10% HF aqueous solution, as the etching speed for the SiO2 is larger, a film 13 is formed with its protruding section having been removed considerably by the etching. Then, on the above film 13, an SiO2 23 is coated and its surface is turned into the smooth one. Therefore, even when a photo resist film is superposed on the film 23 in the following process, the surface is made uniform, there is no step disconnection and a device having excellent characteristics can be obtained.
JP15002879A 1979-11-21 1979-11-21 Manufacture of semiconductor device Pending JPS5673440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15002879A JPS5673440A (en) 1979-11-21 1979-11-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15002879A JPS5673440A (en) 1979-11-21 1979-11-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5673440A true JPS5673440A (en) 1981-06-18

Family

ID=15487911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15002879A Pending JPS5673440A (en) 1979-11-21 1979-11-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5673440A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040004808A (en) * 2002-07-05 2004-01-16 주식회사 하이닉스반도체 Method of etching in a semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5285035A (en) * 1976-01-09 1977-07-15 Hitachi Ltd Method of partially etching semiiconductors
JPS5315073A (en) * 1976-07-28 1978-02-10 Toshiba Corp Production of semiconductor device
JPS5425167A (en) * 1977-07-28 1979-02-24 Mitsubishi Electric Corp Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5285035A (en) * 1976-01-09 1977-07-15 Hitachi Ltd Method of partially etching semiiconductors
JPS5315073A (en) * 1976-07-28 1978-02-10 Toshiba Corp Production of semiconductor device
JPS5425167A (en) * 1977-07-28 1979-02-24 Mitsubishi Electric Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040004808A (en) * 2002-07-05 2004-01-16 주식회사 하이닉스반도체 Method of etching in a semiconductor device

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