JPS5672367A - Circuit for test - Google Patents

Circuit for test

Info

Publication number
JPS5672367A
JPS5672367A JP14927579A JP14927579A JPS5672367A JP S5672367 A JPS5672367 A JP S5672367A JP 14927579 A JP14927579 A JP 14927579A JP 14927579 A JP14927579 A JP 14927579A JP S5672367 A JPS5672367 A JP S5672367A
Authority
JP
Japan
Prior art keywords
receiver
output
shift register
terminal
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14927579A
Other languages
Japanese (ja)
Other versions
JPS634150B2 (en
Inventor
Shozo Toda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14927579A priority Critical patent/JPS5672367A/en
Publication of JPS5672367A publication Critical patent/JPS5672367A/en
Publication of JPS634150B2 publication Critical patent/JPS634150B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To test an object to be tested having a number of input and output terminals with a test machine having less number of terminals, by setting a serial data to a shift register and picking up the data in the shift register externally through the serial data terminal.
CONSTITUTION: Receiver control flags D1, D2...Dn of P-ROM control receivers RV1, RV2...RVn. Taking the receiver control flag as "1", the receiver RVi is at high impedance state and if the receiver control flag Di is "0", the receiver RVi is in active state in which the signal of the flip flop Si2 of a buffer register 7 is output as it is. A parallel terminal Pi is an input terminal when the receiver RVi is at high impedance and it is an output terminal with active state. The shift register 6 is possible for parallel input/output. The parallel output of the shift register 6 is moved to the buffer register 7 with a control signal CK2.
COPYRIGHT: (C)1981,JPO&Japio
JP14927579A 1979-11-17 1979-11-17 Circuit for test Granted JPS5672367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14927579A JPS5672367A (en) 1979-11-17 1979-11-17 Circuit for test

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14927579A JPS5672367A (en) 1979-11-17 1979-11-17 Circuit for test

Publications (2)

Publication Number Publication Date
JPS5672367A true JPS5672367A (en) 1981-06-16
JPS634150B2 JPS634150B2 (en) 1988-01-27

Family

ID=15471648

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14927579A Granted JPS5672367A (en) 1979-11-17 1979-11-17 Circuit for test

Country Status (1)

Country Link
JP (1) JPS5672367A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6262275A (en) * 1985-09-11 1987-03-18 フィリップス　エレクトロニクス　ネムローゼ　フェンノートシャップ Method of testing integrated circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4916351A (en) * 1972-03-27 1974-02-13
JPS5362952A (en) * 1976-11-17 1978-06-05 Fujitsu Ltd Test method for logical device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4916351A (en) * 1972-03-27 1974-02-13
JPS5362952A (en) * 1976-11-17 1978-06-05 Fujitsu Ltd Test method for logical device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6262275A (en) * 1985-09-11 1987-03-18 フィリップス　エレクトロニクス　ネムローゼ　フェンノートシャップ Method of testing integrated circuit

Also Published As

Publication number Publication date
JPS634150B2 (en) 1988-01-27

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