JPS5671885A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS5671885A
JPS5671885A JP14805479A JP14805479A JPS5671885A JP S5671885 A JPS5671885 A JP S5671885A JP 14805479 A JP14805479 A JP 14805479A JP 14805479 A JP14805479 A JP 14805479A JP S5671885 A JPS5671885 A JP S5671885A
Authority
JP
Japan
Prior art keywords
high level
career
prom
write
vcc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14805479A
Other languages
Japanese (ja)
Other versions
JPS639320B2 (en
Inventor
Koichi Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14805479A priority Critical patent/JPS5671885A/en
Publication of JPS5671885A publication Critical patent/JPS5671885A/en
Publication of JPS639320B2 publication Critical patent/JPS639320B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Landscapes

  • Read Only Memory (AREA)

Abstract

PURPOSE:To enable the confirmation of safety for PROM usage, by the storage so that the career of write-in and erase of PROM can be read out with additional memories. CONSTITUTION:PROMs 5, 8, 13... of additional memory section are conductive when the power supply voltage Vcc is at high level and the output is at low level. Then, when Vcc delay is at high level, the output of the latch circuits 6, 10... is at high level, the switches 7, 11... are conductive and the gates of ROMs 5, 8... are grounded. Next, when the write-in voltage VDD is at high level, the data 1 is written in PROM 5 and it remains to be written in even if the voltage Vcc is at a low level. Similarly, data 1 is sequentially written in ROMs 8, 13..., and the career of the number of repetition of erase and write-in is held without holding power supply. The career can be read out via the lines 9, 12... when the Vcc delay is high level, allowing to confirm the safety based on the career of PROM.
JP14805479A 1979-11-15 1979-11-15 Semiconductor memory Granted JPS5671885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14805479A JPS5671885A (en) 1979-11-15 1979-11-15 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14805479A JPS5671885A (en) 1979-11-15 1979-11-15 Semiconductor memory

Publications (2)

Publication Number Publication Date
JPS5671885A true JPS5671885A (en) 1981-06-15
JPS639320B2 JPS639320B2 (en) 1988-02-26

Family

ID=15444121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14805479A Granted JPS5671885A (en) 1979-11-15 1979-11-15 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS5671885A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58215794A (en) * 1982-06-08 1983-12-15 Toshiba Corp Non-volatile memory device
JPS58215795A (en) * 1982-06-08 1983-12-15 Toshiba Corp Non-volatile memory device
JPS6196598A (en) * 1984-10-17 1986-05-15 Fuji Electric Co Ltd Count data memory method of electric erasable p-rom
US5001332A (en) * 1987-12-17 1991-03-19 Siemens Aktiengesellschaft Method and circuit for manipulation-proof devaluation of EEPROMS

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55165499U (en) * 1979-05-10 1980-11-28

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55165499U (en) * 1979-05-10 1980-11-28

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58215794A (en) * 1982-06-08 1983-12-15 Toshiba Corp Non-volatile memory device
JPS58215795A (en) * 1982-06-08 1983-12-15 Toshiba Corp Non-volatile memory device
JPH0552000B2 (en) * 1982-06-08 1993-08-04 Tokyo Shibaura Electric Co
JPS6196598A (en) * 1984-10-17 1986-05-15 Fuji Electric Co Ltd Count data memory method of electric erasable p-rom
US5001332A (en) * 1987-12-17 1991-03-19 Siemens Aktiengesellschaft Method and circuit for manipulation-proof devaluation of EEPROMS

Also Published As

Publication number Publication date
JPS639320B2 (en) 1988-02-26

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