JPS5671879A - Mos type memory integrated circuit - Google Patents

Mos type memory integrated circuit

Info

Publication number
JPS5671879A
JPS5671879A JP14805279A JP14805279A JPS5671879A JP S5671879 A JPS5671879 A JP S5671879A JP 14805279 A JP14805279 A JP 14805279A JP 14805279 A JP14805279 A JP 14805279A JP S5671879 A JPS5671879 A JP S5671879A
Authority
JP
Japan
Prior art keywords
terminal
input
resistor
mos type
type memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14805279A
Other languages
Japanese (ja)
Inventor
Tomoharu Nakamura
Isao Ueki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14805279A priority Critical patent/JPS5671879A/en
Publication of JPS5671879A publication Critical patent/JPS5671879A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To prevent the excessive current and malfunction due to unstable input level, by connecting a resistor to lower the input resistor between the input terminal and power supply terminal or ground terminal, in MOS type memory integrated circuit. CONSTITUTION:A resistor 4 is provided between a line from the input terminal 1 of an input circuit 2 of an MOS type memory IC to an MOS type transistor 3 and ground terminal, or between the input terminal and power supply terminal VDD as shown in dotted lines. Or, a high resistor 33 can externally be mounted at outside the MOS type memory IC30, for example, between the power terminal 31 and the input terminal 32. Even if the input terminal is open, the potential at the input terminal is at 0 level when the resistor 4 is connected to ground terminal and when the resistor 4 is connected to power terminal, it is at 1 level, then excessive current due to unstable input level and malfunction is avoided.
JP14805279A 1979-11-15 1979-11-15 Mos type memory integrated circuit Pending JPS5671879A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14805279A JPS5671879A (en) 1979-11-15 1979-11-15 Mos type memory integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14805279A JPS5671879A (en) 1979-11-15 1979-11-15 Mos type memory integrated circuit

Publications (1)

Publication Number Publication Date
JPS5671879A true JPS5671879A (en) 1981-06-15

Family

ID=15444068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14805279A Pending JPS5671879A (en) 1979-11-15 1979-11-15 Mos type memory integrated circuit

Country Status (1)

Country Link
JP (1) JPS5671879A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01216567A (en) * 1988-02-24 1989-08-30 Nec Corp Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01216567A (en) * 1988-02-24 1989-08-30 Nec Corp Semiconductor integrated circuit

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