JPS5669910A - Level adjustor for pcm signal - Google Patents

Level adjustor for pcm signal

Info

Publication number
JPS5669910A
JPS5669910A JP14825779A JP14825779A JPS5669910A JP S5669910 A JPS5669910 A JP S5669910A JP 14825779 A JP14825779 A JP 14825779A JP 14825779 A JP14825779 A JP 14825779A JP S5669910 A JPS5669910 A JP S5669910A
Authority
JP
Japan
Prior art keywords
down counter
signal
clock
weighting
pcm signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14825779A
Other languages
Japanese (ja)
Inventor
Yoshiji Kusunoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14825779A priority Critical patent/JPS5669910A/en
Publication of JPS5669910A publication Critical patent/JPS5669910A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/002—Control of digital or coded signals

Landscapes

  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To make it easy and accurate to adjust the level of a digital signal by multiplying the output of an up-down counter by the digital signal. CONSTITUTION:A PCM signal, entering multiplier 4 from input terminal 5, is weighted by weighting signal W and outputted to output terminal 6. Weighting signal W is generated by up-down counter 10. The precision of weighting depends upon the number of bits of up-down counter 10. Every time one clock is inputted from clock generating circuit 9, up-down counter 10 counts up or down by one. Switches 7 and 8 are used for assigning the up or down count. The time required for a fade-in and fade-out can be controlled by providing functions of varying the speed and interval of the generation of the clock.
JP14825779A 1979-11-12 1979-11-12 Level adjustor for pcm signal Pending JPS5669910A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14825779A JPS5669910A (en) 1979-11-12 1979-11-12 Level adjustor for pcm signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14825779A JPS5669910A (en) 1979-11-12 1979-11-12 Level adjustor for pcm signal

Publications (1)

Publication Number Publication Date
JPS5669910A true JPS5669910A (en) 1981-06-11

Family

ID=15448729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14825779A Pending JPS5669910A (en) 1979-11-12 1979-11-12 Level adjustor for pcm signal

Country Status (1)

Country Link
JP (1) JPS5669910A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58177682A (en) * 1982-04-14 1983-10-18 カシオ計算機株式会社 Display control system of moving display
JPH0923123A (en) * 1996-08-02 1997-01-21 Sony Corp Device for attenuating digital audio signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58177682A (en) * 1982-04-14 1983-10-18 カシオ計算機株式会社 Display control system of moving display
JPH0923123A (en) * 1996-08-02 1997-01-21 Sony Corp Device for attenuating digital audio signal

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