JPS5668998A - Multiprocessor - Google Patents

Multiprocessor

Info

Publication number
JPS5668998A
JPS5668998A JP14332979A JP14332979A JPS5668998A JP S5668998 A JPS5668998 A JP S5668998A JP 14332979 A JP14332979 A JP 14332979A JP 14332979 A JP14332979 A JP 14332979A JP S5668998 A JPS5668998 A JP S5668998A
Authority
JP
Japan
Prior art keywords
reference request
main memory
processors
case
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14332979A
Other languages
Japanese (ja)
Other versions
JPS607304B2 (en
Inventor
Katsumi Takeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP54143329A priority Critical patent/JPS607304B2/en
Publication of JPS5668998A publication Critical patent/JPS5668998A/en
Publication of JPS607304B2 publication Critical patent/JPS607304B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To detect the mechanical fault through a simultaneous occurrence of the reference request, by giving a control so that the reference request may not be delivered simultaneously to the main memory in case the same main memory is shared with several processors.
CONSTITUTION: The control circuit which decides the reference request to the main memory in the system in which the same main memory is shared with several processors prevents the simultaneous occurrence of the reference request at both the processors 0 and 1. In case the reference request is being processed at the processor 0, the flip-flop 12 is set. Then the reference request generated at the processor 1 is inhibited by the reverse signal 26 of the flip-flop 12 and via the AND gate 14. In case the reference request is being processed at one side when the reference request is generated at the other side, a mechanical fault occurs. Then the AND gates 13 and 16 informs the fault to each processors.
COPYRIGHT: (C)1981,JPO&Japio
JP54143329A 1979-11-07 1979-11-07 multiprocessing device Expired JPS607304B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54143329A JPS607304B2 (en) 1979-11-07 1979-11-07 multiprocessing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54143329A JPS607304B2 (en) 1979-11-07 1979-11-07 multiprocessing device

Publications (2)

Publication Number Publication Date
JPS5668998A true JPS5668998A (en) 1981-06-09
JPS607304B2 JPS607304B2 (en) 1985-02-23

Family

ID=15336241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54143329A Expired JPS607304B2 (en) 1979-11-07 1979-11-07 multiprocessing device

Country Status (1)

Country Link
JP (1) JPS607304B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06235404A (en) * 1993-02-09 1994-08-23 Mitsubishi Heavy Ind Ltd Fluid pressure servo valve

Also Published As

Publication number Publication date
JPS607304B2 (en) 1985-02-23

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