JPS56681A - Electronic clock - Google Patents

Electronic clock

Info

Publication number
JPS56681A
JPS56681A JP7500779A JP7500779A JPS56681A JP S56681 A JPS56681 A JP S56681A JP 7500779 A JP7500779 A JP 7500779A JP 7500779 A JP7500779 A JP 7500779A JP S56681 A JPS56681 A JP S56681A
Authority
JP
Japan
Prior art keywords
control
control circuit
rom
signal
time correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7500779A
Other languages
Japanese (ja)
Inventor
Yasunobu Okano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7500779A priority Critical patent/JPS56681A/en
Publication of JPS56681A publication Critical patent/JPS56681A/en
Pending legal-status Critical Current

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Landscapes

  • Electric Clocks (AREA)

Abstract

PURPOSE: To make it possible to simplify a control circuit and make control diverse, by reading out the ROM matrix according to counting of control clocks to form a dispaly switching signal, a time correction signal, and so on.
CONSTITUTION: Clocks applied to display switching and time correction input terminals SA and SB are counted by counters CA and CB formed by plural FFs respectively. Outputs of counters CA and CB and inversion outputs through an inverter access the memory part constituted by the ROM matrix to output a switching control signal or a time correction control signal from the ROM according to clocks applied to terminal SA or SB. This selective access state of the ROM is reset by applying a clock to forced reset input terminal SC. Since this control circuit is not constituted by individual logical elements, the control circuit is simplified and can correspond to diverse control, and the element arrangement determination time dependent upon mask layout for control circuit generation is shortened.
COPYRIGHT: (C)1981,JPO&Japio
JP7500779A 1979-06-14 1979-06-14 Electronic clock Pending JPS56681A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7500779A JPS56681A (en) 1979-06-14 1979-06-14 Electronic clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7500779A JPS56681A (en) 1979-06-14 1979-06-14 Electronic clock

Publications (1)

Publication Number Publication Date
JPS56681A true JPS56681A (en) 1981-01-07

Family

ID=13563701

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7500779A Pending JPS56681A (en) 1979-06-14 1979-06-14 Electronic clock

Country Status (1)

Country Link
JP (1) JPS56681A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4853875A (en) * 1971-11-08 1973-07-28
JPS51126875A (en) * 1975-04-28 1976-11-05 Toshiba Corp Control system for a clock which works by all the electronic systems
JPS52152760A (en) * 1976-06-14 1977-12-19 Seiko Instr & Electronics Ltd Electronic alarm watch

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4853875A (en) * 1971-11-08 1973-07-28
JPS51126875A (en) * 1975-04-28 1976-11-05 Toshiba Corp Control system for a clock which works by all the electronic systems
JPS52152760A (en) * 1976-06-14 1977-12-19 Seiko Instr & Electronics Ltd Electronic alarm watch

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