JPS5667941A - Forming method of electrode and wiring layer - Google Patents

Forming method of electrode and wiring layer

Info

Publication number
JPS5667941A
JPS5667941A JP14521679A JP14521679A JPS5667941A JP S5667941 A JPS5667941 A JP S5667941A JP 14521679 A JP14521679 A JP 14521679A JP 14521679 A JP14521679 A JP 14521679A JP S5667941 A JPS5667941 A JP S5667941A
Authority
JP
Japan
Prior art keywords
layer
electrode
substrate
ion
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14521679A
Other languages
Japanese (ja)
Inventor
Mikio Kawaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14521679A priority Critical patent/JPS5667941A/en
Publication of JPS5667941A publication Critical patent/JPS5667941A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To eliminate producing a leak by a method wherein an Al layer is installed on a semiconductor substrate by means of an insulation layer, an Al-Si alloy layer is formed by injecting a Si ion into a superficial part and these are etched into a given pattern. CONSTITUTION:After a diffusion layer 2 is formed on a Si substrate 1 taking an oxide film 3 as a mask, an Al layer 4 is evaporated on the entire surface and a si ion layer 5 is injected into a superficial part to form an alloy layer 6. And then, utilizing a resist layer, an etching is performed to a given pattern to form an electrode and a wiring. With this, it is made that Al does not diffuse and permeate into the Si substrate during a heat processing, and a leak due to a Si remnant is not produced, thus, a semiconductor system of high reliability which can maintain the expected characteristic being simply prepared.
JP14521679A 1979-11-08 1979-11-08 Forming method of electrode and wiring layer Pending JPS5667941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14521679A JPS5667941A (en) 1979-11-08 1979-11-08 Forming method of electrode and wiring layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14521679A JPS5667941A (en) 1979-11-08 1979-11-08 Forming method of electrode and wiring layer

Publications (1)

Publication Number Publication Date
JPS5667941A true JPS5667941A (en) 1981-06-08

Family

ID=15380045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14521679A Pending JPS5667941A (en) 1979-11-08 1979-11-08 Forming method of electrode and wiring layer

Country Status (1)

Country Link
JP (1) JPS5667941A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5875869A (en) * 1981-10-06 1983-05-07 アイテイ−テイ−・インダストリ−ズ・インコ−ポレ−テツド Metallization for integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5875869A (en) * 1981-10-06 1983-05-07 アイテイ−テイ−・インダストリ−ズ・インコ−ポレ−テツド Metallization for integrated circuit

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