JPS5666930A - Input circuit - Google Patents

Input circuit

Info

Publication number
JPS5666930A
JPS5666930A JP14348079A JP14348079A JPS5666930A JP S5666930 A JPS5666930 A JP S5666930A JP 14348079 A JP14348079 A JP 14348079A JP 14348079 A JP14348079 A JP 14348079A JP S5666930 A JPS5666930 A JP S5666930A
Authority
JP
Japan
Prior art keywords
state
switch
input terminal
gate
input circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14348079A
Other languages
Japanese (ja)
Inventor
Kazuharu Nishitani
Hiroshi Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14348079A priority Critical patent/JPS5666930A/en
Publication of JPS5666930A publication Critical patent/JPS5666930A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/18—Modifications for indicating state of switch

Landscapes

  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the steady state consumed current, by giving a bias voltage to an input terminal, only when the potential state of the input terminal is required to be known. CONSTITUTION:A control signal CP is produced from a control circuit 1, and it is at ''1'' level when the state of an input terminal 2 is required to be known. Accordingly, when an FET 4 is conductive, and if the switch S is open in this case, the output of a gate 5 is at ''0'', and if the switch S is closed, the output of the gate 5 is at ''1'', allowing to know the state of the switch S.
JP14348079A 1979-11-05 1979-11-05 Input circuit Pending JPS5666930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14348079A JPS5666930A (en) 1979-11-05 1979-11-05 Input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14348079A JPS5666930A (en) 1979-11-05 1979-11-05 Input circuit

Publications (1)

Publication Number Publication Date
JPS5666930A true JPS5666930A (en) 1981-06-05

Family

ID=15339673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14348079A Pending JPS5666930A (en) 1979-11-05 1979-11-05 Input circuit

Country Status (1)

Country Link
JP (1) JPS5666930A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03139879A (en) * 1989-10-25 1991-06-14 Nec Corp Output circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03139879A (en) * 1989-10-25 1991-06-14 Nec Corp Output circuit

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