JPS56663A - Random logic circuit inspecting unit - Google Patents
Random logic circuit inspecting unitInfo
- Publication number
- JPS56663A JPS56663A JP7465679A JP7465679A JPS56663A JP S56663 A JPS56663 A JP S56663A JP 7465679 A JP7465679 A JP 7465679A JP 7465679 A JP7465679 A JP 7465679A JP S56663 A JPS56663 A JP S56663A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- timing
- expected value
- circuit
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE: To realize a high-speed function test, by delaying the expected value transmission timing by an arbitrary time for the input pattern signal transmission timing and by synchronizing the output pattern signal and the expected value signal with each other.
CONSTITUTION: Pulse generating circuit 10 is set to a frequency n-number times as high as timing signal To of the pattern signal of inspected circuit 9, and this pulse signal ϕ is 1/10 frequency-divided through frequency dividing circuit 11 to form input pattern transmission timing signal To. This pulse signal ϕ is divided into n in respect to space through counter circuit 12 and is made into timing signals, which are delayed by one period of timing pulse ϕ for one another successively, through gate circuits G20WG22, and timing signal Tp selected by selecting circuit 13 is used as an expected value transmitting timing signal. Thus, the input pattern is transmitted by timing signal To, and the expected value signal can be transmitted by timing Tp delayed by an arbitrary time, so that the output signal and the expected value signal can be adapted to each other, and consequently, a high-speed function test can be realized.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7465679A JPS56663A (en) | 1979-06-15 | 1979-06-15 | Random logic circuit inspecting unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7465679A JPS56663A (en) | 1979-06-15 | 1979-06-15 | Random logic circuit inspecting unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56663A true JPS56663A (en) | 1981-01-07 |
Family
ID=13553485
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7465679A Pending JPS56663A (en) | 1979-06-15 | 1979-06-15 | Random logic circuit inspecting unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56663A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6181082U (en) * | 1984-10-31 | 1986-05-29 | ||
US4921814A (en) * | 1987-12-28 | 1990-05-01 | Mitsubishi Denki Kabushiki Kaisha | Method of producing an MMIC |
JPH0611544A (en) * | 1993-04-28 | 1994-01-21 | Hitachi Ltd | Test pattern generator |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5381034A (en) * | 1976-12-27 | 1978-07-18 | Hitachi Ltd | Measuring circuit |
-
1979
- 1979-06-15 JP JP7465679A patent/JPS56663A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5381034A (en) * | 1976-12-27 | 1978-07-18 | Hitachi Ltd | Measuring circuit |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6181082U (en) * | 1984-10-31 | 1986-05-29 | ||
US4921814A (en) * | 1987-12-28 | 1990-05-01 | Mitsubishi Denki Kabushiki Kaisha | Method of producing an MMIC |
JPH0611544A (en) * | 1993-04-28 | 1994-01-21 | Hitachi Ltd | Test pattern generator |
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